フォロー
Meikei Ieong
Meikei Ieong
Hong Kong ASTRI (was with TSMC, IBM)
確認したメール アドレス: sloan.mit.edu - ホームページ
タイトル
引用先
引用先
Three-dimensional integrated circuits
AW Topol, DC La Tulipe, L Shi, DJ Frank, K Bernstein, SE Steen, A Kumar, ...
IBM Journal of Research and Development 50 (4.5), 491-506, 2006
9022006
Silicon device scaling to the sub-10-nm regime
M Ieong, B Doris, J Kedzierski, K Rim, M Yang
Science 306 (5704), 2057-2060, 2004
7002004
Integration of strained Ge into advanced CMOS technology
H Shang, M Ieong, JO Chu, KW Guarini
US Patent 7,244,958, 2007
4472007
High performance CMOS fabricated on hybrid substrate with different crystal orientations
M Yang, M Ieong, L Shi, K Chan, V Chan, A Chou, E Gusev, K Jenkins, ...
IEEE International Electron Devices Meeting 2003, 18.7. 1-18.7. 4, 2003
4202003
Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs
K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, ...
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002
4092002
Extension and source/drain design for high-performance FinFET devices
J Kedzierski, M Ieong, E Nowak, TS Kanarsky, Y Zhang, R Roy, D Boyd, ...
IEEE Transactions on Electron Devices 50 (4), 952-958, 2003
3802003
FinFET design considerations based on 3-D simulation and analytical modeling
G Pei, J Kedzierski, P Oldiges, M Ieong, ECC Kan
IEEE Transactions on Electron Devices 49 (8), 1411-1419, 2002
3612002
Three dimensional integrated circuit
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,312,487, 2007
3462007
Strained Si NMOSFETs for high performance CMOS technology
K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, ...
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001
3462001
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
3422005
Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
V Chan, KW Guarini, M Ieong
US Patent 6,821,826, 2004
3032004
Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs
K Rim, K Chan, L Shi, D Boyd, J Ott, N Klymko, F Cardone, L Tai, ...
IEEE International Electron Devices Meeting 2003, 3.1. 1-3.1. 4, 2003
2972003
Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
V Chan, K Guarini, M Ieong
US Patent App. 10/914,433, 2005
2902005
Extreme scaling with ultra-thin Si channel MOSFETs
B Doris, M Ieong, T Kanarsky, Y Zhang, RA Roy, O Dokumaci, Z Ren, ...
Digest. International Electron Devices Meeting,, 267-270, 2002
2882002
High-performance symmetric-gate and CMOS-compatible V/sub t/asymmetric-gate FinFET devices
J Kedzierski, DM Fried, EJ Nowak, T Kanarsky, JH Rankin, H Hanafi, ...
International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001
2882001
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
J Kedzierski, E Nowak, T Kanarsky, Y Zhang, D Boyd, R Carruthers, ...
Digest. International Electron Devices Meeting,, 247-250, 2002
2842002
Three dimensional integrated circuit and method of design
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,723,207, 2010
2572010
Ultra thin body fully-depleted SOI MOSFETs
BB Doris, M Ieong, Z Ren, PM Solomon, M Yang
US Patent 7,459,752, 2008
2542008
Germanium channel MOSFETs: Opportunities and challenges
H Shang, MM Frank, EP Gusev, JO Chu, SW Bedell, KW Guarini, M Ieong
IBM Journal of Research and Development 50 (4.5), 377-386, 2006
2442006
Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model
MK Ieong, PM Solomon, SE Laux, HSP Wong, D Chidambarrao
International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998
2361998
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論文 1–20