Giuseppe Natale
Title
Cited by
Cited by
Year
On how to accelerate iterative stencil loops: a scalable streaming-based approach
R Cattaneo, G Natale, C Sicignano, D Sciuto, MD Santambrogio
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-26, 2015
302015
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops
G Natale, G Stramondo, P Bressana, R Cattaneo, D Sciuto, ...
Proceedings of the 35th International Conference on Computer-Aided Design, 77, 2016
262016
A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA
M Bacis, G Natale, E Del Sozzo, MD Santambrogio
2017 IEEE International Parallel and Distributed Processing Symposium …, 2017
142017
On how to design dataflow FPGA-based accelerators for convolutional neural networks
G Natale, M Bacis, MD Santambrogio
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 639-644, 2017
62017
Heterogeneous exascale supercomputing: The role of cad in the exafpga project
M Rabozzi, G Natale, E Del Sozzo, A Scolari, L Stornaiuolo, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
52017
Optimizing streaming stencil time-step designs via FPGA floorplanning
M Rabozzi, G Natale, B Festa, A Miele, MD Santambrogio
2017 27th international conference on field programmable logic and …, 2017
42017
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils
E Reggiani, G Natale, C Moroni, MD Santambrogio
2018 IEEE International Parallel and Distributed Processing Symposium …, 2018
32018
A CAD open platform for high performance reconfigurable systems in the extra project
M Rabozzi, R Brondolin, G Natale, E Del Sozzo, M Huebner, A Brokalakis, ...
2017 IEEE computer society annual symposium on VLSI (ISVLSI), 368-373, 2017
32017
A framework with cloud integration for cnn acceleration on fpga devices
N Raspa, G Natale, M Bacis, MD Santambrogio
2018 IEEE International Parallel and Distributed Processing Symposium …, 2018
22018
Enabling transparent hardware acceleration on Zynq SoC for scientific computing
L Stornaiuolo, F Carloni, R Pressiani, G Natale, M Santambrogio, D Sciuto
ACM SIGBED Review 17 (1), 30-35, 2020
2020
On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks
G NATALE
Italy, 2019
2019
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains
A Pappalardo, G Natale, MD Santambrogio
2017 Euromicro Conference on Digital System Design (DSD), 151-154, 2017
2017
On how to accelerate iterative stencil loops: a scalable streaming-based approach
C SICIGNANO, G NATALE
Italy, 2015
2015
List of Additional Reviewers
N Anantharajaiah, J Arram, S Baehr, A Becher, JA Belloch, NB Grigore, ...
ASAP 2017 Additional Reviewers
A Erdem, A Scolari, A Ashouri, E Del Sozzo, G Bu, G Natale, H Zhou, ...
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