Device exploration of nanosheet transistors for sub-7-nm technology node D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ... IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017 | 235 | 2017 |
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 123 | 2018 |
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ... 2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017 | 122 | 2017 |
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017 | 102 | 2017 |
Self-heating on bulk FinFET from 14nm down to 7nm node D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ... 2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015 | 95 | 2015 |
Novel forksheet device architecture as ultimate logic scaling device towards 2nm P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ... 2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019 | 94 | 2019 |
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications A Veloso, T Huynh-Bao, P Matagne, D Jang, G Eneman, N Horiguchi, ... Solid-State Electronics 168, 107736, 2020 | 82 | 2020 |
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ... 2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016 | 77 | 2016 |
Low-frequency noise in junctionless multigate transistors D Jang, JW Lee, CW Lee, JP Colinge, L Montès, JI Lee, GT Kim, ... Applied Physics Letters 98 (13), 2011 | 69 | 2011 |
Enabling sub-5nm CMOS technology scaling thinner and taller! J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ... 2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019 | 68 | 2019 |
Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires K Tachi, M Casse, D Jang, C Dupre, A Hubert, N Vulliet, V Maffini-Alvaro, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 61 | 2009 |
Nanoneedle transistor-based sensors for the selective detection of intracellular calcium ions D Son, SY Park, B Kim, JT Koh, TH Kim, S An, D Jang, GT Kim, W Jhe, ... ACS nano 5 (5), 3888-3895, 2011 | 58 | 2011 |
Mobility analysis of surface roughness scattering in FinFET devices JW Lee, D Jang, M Mouis, GT Kim, T Chiarella, T Hoffmann, G Ghibaudo Solid-State Electronics 62 (1), 195-201, 2011 | 52 | 2011 |
Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 51 | 2021 |
DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies MG Bardon, P Wuytens, LÅ Ragnarsson, G Mirabelli, D Jang, G Willems, ... 2020 IEEE International Electron Devices Meeting (IEDM), 41.4. 1-41.4. 4, 2020 | 50 | 2020 |
Holisitic device exploration for 7nm node P Raghavan, MG Bardon, D Jang, P Schuddinck, D Yakimets, J Ryckaert, ... 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-5, 2015 | 48 | 2015 |
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017 | 47 | 2017 |
Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ... 2019 Symposium on VLSI Technology, T204-T205, 2019 | 44 | 2019 |
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells MG Bardon, Y Sherazi, D Jang, D Yakimets, P Schuddinck, R Baert, ... 2018 IEEE Symposium on VLSI Technology, 143-144, 2018 | 44 | 2018 |
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling MG Bardon, P Schuddinck, P Raghavan, D Jang, D Yakimets, A Mercha, ... 2015 International Conference on IC Design & Technology (ICICDT), 1-4, 2015 | 43 | 2015 |