Amit Ranjan Trivedi
Amit Ranjan Trivedi
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Exploring tunnel-FET for ultra low power analog applications: A case study on operational transconductance amplifier
AR Trivedi, S Carlo, S Mukhopadhyay
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2013
RF SOI switch FET design and modeling tradeoffs for GSM applications
S Parthasarathy, A Trivedi, S Sirohi, R Groves, M Olsen, YS Chauhan, ...
2010 23rd International Conference on VLSI Design, 194-199, 2010
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM
T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan
IEEE Electron Device Letters 38 (8), 1161-1164, 2017
Application of silicon-germanium source tunnel-fet to enable ultralow power cellular neural network-based associative memory
AR Trivedi, S Datta, S Mukhopadhyay
IEEE Transactions on Electron Devices 61 (11), 3707-3715, 2014
Ultra-low power electronics with Si/Ge tunnel FET
AR Trivedi, MF Amir, S Mukhopadhyay
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
Low power restricted Boltzmann machine using mixed-mode magneto-tunneling junctions
S Nasrin, JL Drobitch, S Bandyopadhyay, AR Trivedi
IEEE Electron Device Letters 40 (2), 345-348, 2019
Potential of ultralow-power cellular neural image processing with Si/Ge tunnel FET
AR Trivedi, S Mukhopadhyay
IEEE Transactions on Nanotechnology 13 (4), 627-629, 2014
Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory—Part II
SD Manasi, MM Al-Rashid, J Atulasimha, S Bandyopadhyay, AR Trivedi
IEEE Transactions of Electron Devices, 2017
A Simulation Study of Oxygen Vacancy-Induced Variability in /Metal Gated SOI FinFET
AR Trivedi, T Ando, A Singhee, P Kerber, E Acar, DJ Frank, ...
IEEE Transactions on Electron Devices 61 (5), 1262-1269, 2014
Negative gate transconductance in gate/source overlapped heterojunction tunnel FET and application to single transistor phase encoder
AR Trivedi, KZ Ahmed, S Mukhopadhyay
IEEE Electron Device Letters 36 (2), 201-203, 2015
Through-oxide-via-induced back-gate effect in 3-D integrated FDSOI devices
AR Trivedi, S Mukhopadhyay
IEEE electron device letters 32 (8), 1020-1022, 2011
Exploration of Si/Ge tunnel FET bit cells for ultra-low power embedded memory
MF Amir, AR Trivedi, S Mukhopadhyay
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (2 …, 2016
Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity
AR Trivedi, R Pandey, H Liu, S Datta, S Mukhopadhyay
2015 IEEE International Electron Devices Meeting (IEDM), 17.8. 1-17.8. 4, 2015
Single spin Toffoli–Fredkin logic gate
AR Trivedi, S Bandyopadhyay
Journal of Applied Physics 103 (10), 104311, 2008
Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks
AR Trivedi, W Yueh, S Mukhopadhyay
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging …, 2011
Compact modeling of partially depleted silicon-on-insulator drain-extended MOSFET (DEMOSFET) including high-voltage and floating-body effects
TK Agarwal, AR Trivedi, V Subramanian, MJ Kumar
IEEE transactions on electron devices 58 (10), 3485-3493, 2011
Performance and robustness of 3-D integrated SRAM considering tier-to-tier thermal and supply crosstalk
W Yueh, S Chatterjee, AR Trivedi, S Mukhopadhyay
IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (6 …, 2013
Switching voltage, dynamic power dissipation and on-to-off conductance ratio of a spin field effect transistor
AR Trivedi, S Bandyopadhyay, M Cahay
IET circuits, devices & systems 1 (6), 395-400, 2007
Area and energy-efficient physically unclonable function based on k-winners-take-all
T Dhar, AR Trivedi
Electronics Letters 52 (24), 1978-1980, 2016
Gate/source-overlapped heterojunction Tunnel FET-based LAMSTAR neural network and its Application to EEG Signal Classification
SD Manasi, AR Trivedi
2016 International Joint Conference on Neural Networks (IJCNN), 955-962, 2016
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