Won-Joo Yun
Won-Joo Yun
Principal Engineer, DRAM Design Team, Memory Business, Samsung Electronics
Verified email at ieee.org
Title
Cited by
Cited by
Year
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
WJ Yun, HW Lee, D Shin, S Kim
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19 (9 …, 2011
372011
A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology
WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
372008
DLL circuit and method of controlling the same
DS Shin, H Lee, WJ Yun
US Patent 7,598,783, 2009
322009
DLL circuit having duty cycle correction and method of controlling the same
WJ Yun, HW Lee
US Patent 7,821,310, 2010
282010
A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution
K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ...
IEEE Journal of Solid-State Circuits 52 (1), 250-260, 2016
242016
18.2 A 1.2 V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution
K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 316-317, 2016
242016
Delay-locked loop apparatus and delay-locked method
WJ Yun, HW Lee
US Patent 7,560,963, 2009
192009
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line
WJ Yun, S Nakano, W Mizuhara, A Kosuge, N Miura, H Ishikuro, T Kuroda
2012 IEEE International Solid-State Circuits Conference, 52-54, 2012
182012
Semiconductor memory apparatus
HW Lee, WJ Yun
US Patent 7,800,422, 2010
182010
Data output strobe signal generating circuit and semiconductor memory apparatus having the same
WJ Yun, H Lee
US Patent 7,633,324, 2009
182009
Power-down mode control apparatus and DLL circuit having the same
DSS H.-W. Lee, Won-Joo Yun
US Patent 7,868,673, 2011
17*2011
Delay locked loop apparatus
WJ Yun, HW Lee
US Patent 7,830,186, 2010
152010
Cutting tool with linear oscillating drive
H Bollinger, M Keller
US Patent 6,739,059, 2004
14*2004
Delay locked loop apparatus
HWL Won-Joo Yun
US Patent 8,120,397, 2012
11*2012
Semiconductor memory device
H Lee, WJ Yun
US Patent 7,535,270, 2009
112009
Duty cycle correcting circuit and method
DS Shin, H Lee, WJ Yun
US Patent App. 12/200,747, 2009
102009
Multi-slew-rate output driver and optimized impedance-calibration circuit for 66nm 3.0 Gb/s/pin DRAM interface
DU Lee, SD Kang, NK Park, HW Lee, YK Choi, JW Lee, SW Kwack, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
102008
Delay-locked loop apparatus adjusting internal clock signal in synchronization with external clock signal
WJ Yun, HW Lee
US Patent App. 11/683,528, 2008
102008
Duty cycle correcting circuit and method of correcting a duty cycle
HWL Won-Joo Yun
US Patent 8,228,104, 2012
9*2012
Semiconductor integrated circuit
WJ Yun, HW Lee, KH Kim
US Patent 7,928,783, 2011
92011
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Articles 1–20