| An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture H Makino, Y Nakase, H Suzuki, H Morinaka, H Shinohara, K Mashiko IEEE Journal of Solid-State Circuits 31 (6), 773-783, 1996 | 230 | 1996 |
| Leading-zero anticipatory logic for high-speed floating point addition H Suzuki, H Morinaka, H Makino, Y Nakase, K Mashiko, T Sumi IEEE Journal of Solid-State Circuits 31 (8), 1157-1164, 1996 | 163 | 1996 |
| Gate array semiconductor device K Ueda, T Hirota, Y Wada, K Mashiko US Patent 6,084,255, 2000 | 112 | 2000 |
| Random access memory with a plurality amplifier groups for reading and writing in normal and test modes K Furutani, K Mashiko, K Arimoto, N Matsumoto, Y Matsuda US Patent 5,636,163, 1997 | 97 | 1997 |
| Dynamic random access memory device with staggered refresh K Mashiko US Patent 4,912,678, 1990 | 87 | 1990 |
| A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture Y Arima, K Mashiko, K Okada, T Yamada, A Maeda, H Notani, H Kondoh, ... IEEE journal of solid-state circuits 26 (11), 1637-1644, 1991 | 76 | 1991 |
| Semiconductor neural network including photosensitive coupling elements K Mashiko US Patent 4,988,891, 1991 | 74 | 1991 |
| A self-learning neural network chip with 125 neurons and 10 K self-organization synapses Y Arima, K Mashiko, K Okada, T Yamada, A Maeda, H Kondoh, S Kayano IEEE journal of solid-state circuits 26 (4), 607-611, 1991 | 63 | 1991 |
| Random access memory device operable in a normal mode and in a test mode K Furutani, K Mashiko, K Arimoto, N Matsumoto, Y Matsuda US Patent 4,873,669, 1989 | 59 | 1989 |
| Semiconductor integrated circuit having reduced current leakage and high speed K Mashiko US Patent 6,034,563, 2000 | 58 | 2000 |
| Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate K Mashiko, K Ueda, Y Wada US Patent 6,177,826, 2001 | 56 | 2001 |
| Substrate-bias Effect and Source-drain Breakdown Characteristics in Body-tied Short-channel SOI MOSFET's S Maeda, Y Hirano, Y Yamaguchi, T Iwamatsu, T Ipposhi, K Ueda, ... IEEE Transactions on Electron Devices 46 (1), 151-158, 1999 | 56 | 1999 |
| Semiconductor integrated circuit K Mashiko, K Ueda, H Suzuki, H Morinaka US Patent 5,781,062, 1998 | 55 | 1998 |
| A 1.9-GHz single chip IF transceiver for digital cordless phones H Sato, K Kashiwagi, K Niwano, T Iga, T Ikeda, K Mashiko, T Sumi, ... IEEE Journal of Solid-State Circuits 31 (12), 1974-1980, 1996 | 49 | 1996 |
| Dynamic type semiconductor memory device having an error checking and correcting circuit K Arimoto, K Furutani, K Mashiko US Patent 5,012,472, 1991 | 40 | 1991 |
| Shared sense amplifier semiconductor memory N Matsumoto, T Kobayashi, K Mashiko US Patent 4,982,370, 1991 | 40 | 1991 |
| Semiconductor neural network and operating method thereof K Mashiko US Patent 5,475,794, 1995 | 39 | 1995 |
| A 64 bit carry look-ahead CMOS adder using Modified Carry Select H Morinaka, H Makino, Y Nakase, H Suzuki, K Mashiko Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 585-588, 1995 | 37 | 1995 |
| Semiconductor memory device K Furutani, K Mashiko, K Arimoto, N Matsumoto, Y Matsuda US Patent 4,849,938, 1989 | 37 | 1989 |
| A 64-bit carry look ahead adder using pass transistor BiCMOS gates K Ueda, H Suzuki, K Suda, H Shinohara, K Mashiko IEEE journal of Solid-State circuits 31 (6), 810-818, 1996 | 33 | 1996 |
Hiroshi MakinoOsaka Institute of TechnologyVerified email at oit.ac.jp
