| A 3.8-ns CMOS 16* 16-b multiplier using complementary pass-transistor logic K Yano, T Yamanaka, T Nishida, M Saito, K Shimohigashi, A Shimizu IEEE journal of solid-state circuits 25 (2), 388-395, 1990 | 725 | 1990 |
| Room-temperature single-electron memory K Yano, T Ishii, T Hashimoto, T Kobayashi, F Murai, K Seki IEEE transactions on electron devices 41 (9), 1628-1638, 1994 | 636 | 1994 |
| Top-down pass-transistor logic design K Yano, Y Sasaki, K Rikino, K Seki IEEE journal of solid-state circuits 31 (6), 792-803, 1996 | 393 | 1996 |
| Single-electron memory for giga-to-tera bit storage K Yano, T Ishii, T Sano, T Mine, F Murai, T Hashimoto, T Kobayashi, ... Proceedings of the IEEE 87 (4), 633-651, 1999 | 266 | 1999 |
| Semiconductor integrated circuit device and production method thereof K Yano, Y Sasaki US Patent 5,581,202, 1996 | 203 | 1996 |
| A poly-silicon TFT with a sub-5-nm thick channel for low-power gain cell memory in mobile applications T Ishii, T Osabe, T Mine, T Sano, B Atwood, K Yano IEEE Transactions on Electron Devices 51 (11), 1805-1810, 2004 | 194 | 2004 |
| Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit N Katoh, K Yano, Y Akita, M Hiraki US Patent 6,769,110, 2004 | 174 | 2004 |
| Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment M Miyazaki, H Tanaka, G Ono, T Nagano, N Ohkubo, T Kawahara, K Yano Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 130 | 2003 |
| Semiconductor integrated circuit for low power and high speed operation I Kono, K Yano, N Kato US Patent 6,515,521, 2003 | 128 | 2003 |
| Predictability of conversation partners T Takaguchi, M Nakamura, N Sato, K Yano, N Masuda Physical Review X 1 (1), 011008, 2011 | 116 | 2011 |
| Performance and hot-carrier effects of small CRYO-CMOS devices M Aoki, S Hanamura, T Masuhara, K Yano IEEE transactions on electron devices 34 (1), 8-18, 1987 | 100 | 1987 |
| Transport characteristics of polycrystalline‐silicon wire influenced by single‐electron charging at room temperature K Yano, T Ishii, T Hashimoto, T Kobayashi, F Murai, K Seki Applied physics letters 67 (6), 828-830, 1995 | 91 | 1995 |
| Semiconductor memory device T Sano, T Ishii, K Yano, T Mine US Patent 6,040,605, 2000 | 81 | 2000 |
| A 15--15 mm, 1 μA, reliable sensor-net module: enabling application-specific nodes S Yamashita, T Shimura, K Aiki, K Ara, Y Ogata, I Shimokawa, T Tanaka, ... Proceedings of the 5th international conference on Information processing in …, 2006 | 77 | 2006 |
| Sensible organizations: Changing our businesses and work styles through sensor data K Ara, N Kanehira, DO Olguin, BN Waber, T Kim, A Mohan, P Gloor, ... Journal of Information Processing 16, 1-12, 2008 | 70 | 2008 |
| Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure T Ishii, K Yano, T Mine US Patent 6,576,943, 2003 | 69 | 2003 |
| Semiconductor memories B Atwood, K Yano, T Ishii, T Osabe, K Yanagisawa, T Sakata US Patent 6,787,835, 2004 | 65 | 2004 |
| Semiconductor memory device T Ishii, K Yano US Patent 6,646,300, 2003 | 58 | 2003 |
| Single-electron-memory integrated circuit for giga-to-tera bit storage K Yano, T Ishii, T Sano, T Mine, F Murai, K Seki 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical …, 1996 | 56 | 1996 |
| A 128 Mb early prototype for gigascale single-electron memories K Yano, T Ishii, T Sane, T Mine, F Murai, T Kure, K Seki 1998 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1998 | 52 | 1998 |
Noboru KoshizukaProfessor, Interfaculty Initiative in Information Studies, The University of TokyoVerified email at koshizuka-lab.org
