Analytical model of subthreshold current and slope for asymmetric 4-T and 3-T double-gate MOSFETs A Dey, A Chakravorty, N DasGupta, A DasGupta IEEE transactions on electron devices 55 (12), 3442-3449, 2008 | 99 | 2008 |
Stability of IZO and a-Si:H TFTs Processed at Low Temperature (200) K Kaftanoglu, SM Venugopal, M Marrs, A Dey, EJ Bawolek, DR Allee, ... Journal of Display Technology 7 (6), 339-343, 2011 | 39 | 2011 |
Symmetric linearization method for double-gate and surrounding-gate MOSFET models G Dessai, A Dey, G Gildenblat, GDJ Smit Solid-state electronics 53 (5), 548-556, 2009 | 31 | 2009 |
Improved circuits for microchip identification using SRAM mismatch S Chellappa, A Dey, LT Clark 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 26 | 2011 |
CMOS TFT op-amps: Performance and limitations A Dey, A Avendanno, S Venugopal, DR Allee, M Quevedo, B Gnade IEEE electron device letters 32 (5), 650-652, 2011 | 25 | 2011 |
Amorphous silicon 5 bit flash analog to digital converter A Dey, DR Allee Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 14 | 2012 |
Effect of mechanical and electromechanical stress on a-ZIO TFTs A Dey, A Indluru, SM Venugopal, DR Allee, TL Alford IEEE electron device letters 31 (12), 1416-1418, 2010 | 14 | 2010 |
Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs A Dey, DR Allee, LT Clark Solid-state electronics 62 (1), 19-24, 2011 | 12 | 2011 |
Amorphous silicon 7 bit digital to analog converter on PEN A Dey, H Song, T Ahmed, SM Venugopal, DR Allee IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 5 | 2010 |
Jitter transfer function model and VLSI jitter filter circuits H Song, J Song, A Dey, Y Song 23rd IEEE International SOC Conference, 48-51, 2010 | 3 | 2010 |
Amplifiers with depletion and enhancement mode thin film transistors and related methods SM Venugopal, A Dey, DR Allee US Patent 8,319,561, 2012 | 2 | 2012 |
Amplifiers with depletion and enhancement mode thin film transistors and related methods SM Venugopal, A Dey, DR Allee US Patent 8,319,561, 2012 | 2 | 2012 |
Modeling of ISI in high speed serial I/Os terminated with discontinuities A Dey, HJ Song 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging …, 2011 | 2 | 2011 |
Complementary biasing circuits and related methods A Dey US Patent 9,035,692, 2015 | 1 | 2015 |
Amorphous silicon current steering digital to analog converter A Dey, DR Allee 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 1 | 2011 |
Stability improvement of a-ZIO TFT circuits using low temperature anneal A Dey, DR Allee 2011 International Reliability Physics Symposium, TF. 1.1-TF. 1.4, 2011 | | 2011 |
Mixed Signal Design in Thin Film Transistors A Dey Arizona State University, 2011 | | 2011 |
FLEXIBLE INTERFACE ELECTRONICS FOR LARGE AREA SENSORS A Dey, SM Venugopal, H Song, DR Allee, AE Avendano-Bolivar, ... | | |
An Improved Analytic Solution to Surface Potential for Un-doped Surrounding-Gate MOSFET A Dey, A DasGupta | | |