Pouya Hashemi
Pouya Hashemi
IBM Manager and Research Staff Member
確認したメール アドレス: us.ibm.com - ホームページ
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ...
2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012
Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter
P Hashemi, L Gomez, JL Hoyt
IEEE electron device letters 30 (4), 401-403, 2009
Enhanced hole transport in short-channel strained-SiGe p-MOSFETs
L Gomez, P Hashemi, JL Hoyt
IEEE transactions on electron devices 56 (11), 2644-2651, 2009
Ultrathin Strained-Ge Channel P-MOSFETs With High-/Metal Gate and Sub-1-nm Equivalent Oxide Thickness
P Hashemi, W Chern, HS Lee, JT Teherani, Y Zhu, J Gonsalvez, ...
IEEE electron device letters 33 (7), 943-945, 2012
Nanowire transistor structures with merged source/drain regions using auxiliary pillars
P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,257,527, 2016
Enhanced hole mobility in high Ge content asymmetrically strained-SiGe p-MOSFETs
L Gomez, CN Chlairigh, P Hashemi, JL Hoyt
IEEE Electron Device Letters 31 (8), 782-784, 2010
Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
A Khakifirooz, K Cheng, T Nagumo, N Loubet, T Adam, A Reznicek, ...
2012 Symposium on VLSI technology (VLSIT), 117-118, 2012
Vertical transistor with air gap spacers
K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,443,982, 2016
Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs
P Hashemi, L Gomez, M Canonico, JL Hoyt
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Strained FinFET by epitaxial stressor independent of gate pitch
K Cheng, P Hashemi, A Khakifirooz, A Reznicek, CVVS Surisetty
US Patent 9,647,113, 2017
Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI fin pFETs
V Deshpande, V Djara, E O'Connor, P Hashemi, K Balakrishnan, M Sousa, ...
2015 IEEE International Electron Devices Meeting (IEDM), 8.8. 1-8.8. 4, 2015
Thin-film Si1− xGex HIT solar cells
SA Hadi, P Hashemi, N DiLello, E Polyzoeva, A Nayfeh, JL Hoyt
Solar Energy 103, 154-159, 2014
High Hole-Mobility Strained-P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness
P Hashemi, JL Hoyt
IEEE electron device letters 33 (2), 173-175, 2011
Thin film a-si/c-si1-xGex/c-si heterojunction solar cells: Design and material quality requirements
SA Hadi, P Hashemi, A Nayfeh, J Hoyt
ECS Transactions 41 (4), 3, 2011
Asymmetric strain in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructures on insulator
P Hashemi, L Gomez, JL Hoyt, MD Robertson, M Canonico
Applied Physics Letters 91 (8), 083109, 2007
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Fabrication of nano-sheet transistors with different threshold voltages
K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,653,289, 2017
Perfectly symmetric gate-all-around FET on suspended nanowire
K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,853,166, 2017
Channel-last replacement metal-gate vertical field effect transistor
K Balakrishnan, K Cheng, P Hashemi, A Reznicek
US Patent 9,525,064, 2016
High-mobility high-Ge-content Si1−xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å …
P Hashemi, T Ando, K Balakrishnan, J Bruley, S Engelmann, JA Ott, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), T16-T17, 2015
論文 1–20