| 28nm FDSOI technology platform for high-speed low-voltage digital applications N Planes, O Weber, V Barral, S Haendler, D Noblet, D Croain, M Bocat, ... VLSI Technology (VLSIT), 2012 Symposium on, 133-134, 2012 | 519 | 2012 |
| NBTI degradation: From transistor to SRAM arrays V Huard, C Parthasarathy, C Guerin, T Valentin, E Pion, M Mammasse, ... Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, 289-300, 2008 | 178 | 2008 |
| A new combined methodology for write-margin extraction of advanced SRAM N Gierczynski, B Borot, N Planes, H Brut Microelectronic Test Structures, 2007. ICMTS'07. IEEE International …, 2007 | 92 | 2007 |
| Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology P Flatresse, B Giraud, JP Noel, B Pelloux-Prayer, F Giner, DK Arora, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 …, 2013 | 88 | 2013 |
| Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology C Fenouillet-Beranger, P Perreau, L Pham-Nguyen, S Denorme, ... Electron Devices Meeting (IEDM), 2009 IEEE International, 1-4, 2009 | 63 | 2009 |
| A functional 0.69/spl mu/m/sup 2/embedded 6T-SRAM bit cell for 65 nm CMOS platform F Arnaud, F Boeuf, F Salvetti, D Lenoble, F Wacquant, C Regnier, P Morin, ... VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 65-66, 2003 | 60 | 2003 |
| Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications S Makovejev, BK Esfeh, V Barral, N Planes, M Haond, D Flandre, ... Solid-State Electronics 108, 47-52, 2015 | 59 | 2015 |
| Strain effect in silicon-on-insulator materials: Investigation with optical phonons J Camassel, LA Falkovsky, N Planes Physical Review B 63 (3), 035309, 2000 | 53 | 2000 |
| Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements BK Esfeh, V Kilchytska, V Barral, N Planes, M Haond, D Flandre, ... Solid-State Electronics 117, 130-137, 2016 | 51 | 2016 |
| 28nm node bulk vs FDSOI reliability comparison X Federspiel, D Angot, M Rafik, F Cacho, A Bajolet, N Planes, D Roy, ... Reliability Physics Symposium (IRPS), 2012 IEEE International, 3B. 1.1-3B. 1.4, 2012 | 51 | 2012 |
| Low cost 65nm cmos platform for low power & general purpose applications F Arnaud, B Duriez, B Tavel, L Pain, J Todeschini, M Jurdit, Y Laplanche, ... VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, 10-11, 2004 | 46 | 2004 |
| Switching energy efficiency optimization for advanced CPU thanks to UTBB technology F Arnaud, N Planes, O Weber, V Barral, S Haendler, P Flatresse, F Nyer Electron Devices Meeting (IEDM), 2012 IEEE International, 3.2. 1-3.2. 4, 2012 | 45 | 2012 |
| First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration D Golanski, P Fonteneau, C Fenouillet-Beranger, A Cros, F Monsieur, ... VLSI Circuits (VLSIC), 2013 Symposium on, T124-T125, 2013 | 44 | 2013 |
| Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors EG Ioannidis, S Haendler, A Bajolet, T Pahron, N Planes, F Arnaud, ... Electron Devices Meeting (IEDM), 2011 IEEE International, 18.6. 1-18.6. 4, 2011 | 44 | 2011 |
| FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs R Ranica, N Planes, O Weber, O Thomas, S Haendler, D Noblet, D Croain, ... VLSI Technology (VLSIT), 2013 Symposium on, T210-T211, 2013 | 43 | 2013 |
| SOI integrated circuit comprising adjacent cells of different types O Thomas, J Mazurier, N Planes, O Weber US Patent 9,190,334, 2015 | 42 | 2015 |
| Managing SRAM reliability from bitcell to library level V Huard, R Chevallier, C Parthasarathy, A Mishra, N Ruiz-Amador, ... Reliability Physics Symposium (IRPS), 2010 IEEE International, 655-664, 2010 | 42 | 2010 |
| 0.248/spl mu/m/sup 2/and 0.334/spl mu/m/sup 2/conventional bulk 6T-SRAM bit-cells for 45nm node low cost-general purpose applications F Boeuf, F Arnaud, C Boccaccio, F Salvetti, J Todeschini, L Pain, M Jurdit, ... VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, 130-131, 2005 | 36 | 2005 |
| SON (Silicon-on-nothing) technological CMOS platform: Highly performant devices and SRAM Cells S Monfray, D Chanemougame, S Borel, A Talbot, F Leverd, N Planes, ... Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International …, 2004 | 29 | 2004 |
| Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI S Makovejev, N Planes, M Haond, D Flandre, JP Raskin, V Kilchytska Solid-State Electronics 115, 219-224, 2016 | 26 | 2016 |
