Toshihiko Miyashita
Toshihiko Miyashita
確認したメール アドレス: micron.com
タイトル
引用先
引用先
Memory cell array, method of producing the same, and semiconductor memory device using the same
E Yoshida, T Tanaka, T Miyashita
US Patent 7,671,417, 2010
1422010
Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM
T Tanaka, E Yoshida, T Miyashita
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
1402004
A 16nm FinFET CMOS technology for mobile SoC and computing applications
SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, M Liang, ...
2013 IEEE International Electron Devices Meeting, 9.1. 1-9.1. 4, 2013
1392013
Manufacturing method of semiconductor device suppressing short-channel effect
T Miyashita, K Suzuki
US Patent 7,223,646, 2007
1232007
Manufacturing method of semiconductor device suppressing short-channel effect
T Miyashita, K Suzuki
US Patent 7,312,500, 2007
1152007
A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications
SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, CH Tsai, ...
2016 IEEE International Electron Devices Meeting (IEDM), 2.6. 1-2.6. 4, 2016
732016
An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance …
SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, SZ Chang, ...
2014 IEEE International Electron Devices Meeting, 3.1. 1-3.1. 4, 2014
642014
Electron Devices Meeting (IEDM), 2011 IEEE International
S Gupta, R Chen, B Magyari-Kope, H Lin, B Yang, A Nainani, Y Nishi, ...
IEEE, 2011
322011
High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS …
T Miyashita, K Ikeda, YS Kim, T Yamamoto, Y Sambonsugi, H Ochimizu, ...
2007 IEEE International Electron Devices Meeting, 251-254, 2007
292007
A study of highly scalable DG-FinDRAM
E Yoshida, T Miyashita, T Tanaka
IEEE electron device letters 26 (9), 655-657, 2005
292005
Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology
T Yamamoto, T Kubo, T Sukegawa, E Takii, Y Shimamune, N Tamura, ...
2007 IEEE International Electron Devices Meeting, 143-146, 2007
222007
Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node
SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, CH Chang, VS Chang, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
152016
Experimental evaluation of depth-dependent lateral standard deviation for various ions in a-Si from one-dimensional tilted implantation profiles
T Miyashita, K Suzuki
IEEE Transactions on Electron Devices 46 (9), 1824-1828, 1999
141999
Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications
T Miyashita, T Owada, A Hatada, Y Hayami, K Ookoshi, T Mori, H Kurata, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
122008
Advantages of a new scheme of junction profile engineering with laser spike annealing and its integration into a 45-nm node high performance CMOS technology
T Yamamoto, T Kubo, T Sukegawa, A Katakami, Y Shimamune, N Tamura, ...
2007 IEEE Symposium on VLSI Technology, 122-123, 2007
112007
High-performance low operation power transistor for 45 nm node universal applications
M Shima, K Okabe, A Yamaguchi, T Sakoda, K Kawamura, S Pidin, ...
VLSI Symp. Tech. Dig., 156-157, 2006
102006
Manufacturing method of a MOS transistor using a sidewall spacer
T Miyashita
US Patent 8,741,711, 2014
82014
Semiconductor device and method of manufacturing same
T Miyashita, K Ikeda
US Patent App. 12/561,841, 2010
82010
45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications
M Okuno, K Okabe, T Sakuma, K Suzuki, T Miyashita, T Yao, H Morioka, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 52-55, 2005
82005
High voltage I/O FinFET device optimization for 16nm system-on-a-chip (SoC) technology
T Miyashita, KC Kwong, PH Wu, BC Hsu, PN Chen, CH Tsai, MC Chiang, ...
2015 Symposium on VLSI Technology (VLSI Technology), T152-T153, 2015
62015
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論文 1–20