| Performance evaluation of a vector supercomputer SX-Aurora TSUBASA K Komatsu, S Momose, Y Isobe, O Watanabe, A Musa, M Yokokawa, ... SC18: International Conference for High Performance Computing, Networking …, 2018 | 24 | 2018 |
| A cache-aware thread scheduling policy for multi-core processors M Sato, I Kotera, R Egawa, H Takizawa, H Kobayashi Proceedings of the IASTED International Conference on Parallel and …, 2009 | 12 | 2009 |
| A voting-based working set assessment scheme for dynamic cache resizing mechanisms M Sato, R Egawa, H Takizawa, H Kobayashi 2010 IEEE International Conference on Computer Design, 98-105, 2010 | 8 | 2010 |
| An adaptive demotion policy for high-associativity caches J Tada, M Sato, R Egawa Proceedings of the 8th International Symposium on Highly Efficient …, 2017 | 6 | 2017 |
| Vertically integrated processor and memory module design for vector supercomputers R Egawa, M Sato, J Tada, H Kobayashi 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013 | 3 | 2013 |
| A flexible insertion policy for dynamic cache resizing mechanisms M Sato, Y Tobo, R Egawa, H Takizawa, H Kobayashi 2013 IEEE COOL Chips XVI, 1-3, 2013 | 3 | 2013 |
| Search space reduction for parameter tuning of a tsunami simulation on the intel knights landing processor K Komatsu, T Kishitani, M Sato, A Musa, H Kobayashi 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018 | 2 | 2018 |
| Effect of retransmissions in mobile agent communications under unstable network conditions M Sato, M Urakami, H Matsuno 7th International Conference on Mobile Data Management (MDM'06), 132-132, 2006 | 2 | 2006 |
| Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA O Watanabe, Y Hougi, K Komatsu, M Sato, A Musa, H Kobayashi 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC …, 2019 | 1 | 2019 |
| An adjacent-line-merging writeback scheme for stt-ram-based last-level caches M Sato, Y Shoji, Z Sakai, R Egawa, H Kobayashi IEEE Transactions on Multi-Scale Computing Systems 4 (4), 593-604, 2018 | 1 | 2018 |
| An adjacent-line-merging writeback scheme for STT-RAM last-level caches M Sato, Z Sakai, R Egawa, H Kobayashi 2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-2, 2017 | 1 | 2017 |
| An application-adaptive data allocation method for multi-channel memory T Toyoshima, M Sato, R Egawa, H Kobayashi 2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2017 | 1 | 2017 |
| A cache partitioning mechanism to protect shared data for CMPs M Sato, S Nishimura, R Egawa, H Takizawa, H Kobayashi 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-2, 2016 | 1 | 2016 |
| An energy-efficient dynamic memory address mapping mechanism M Sato, C Han, K Komatsu, R Egawa, H Takizawa, H Kobayashi 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII), 1-3, 2015 | 1 | 2015 |
| On-chip checkpointing with 3D-stacked memories M Sato, R Egawa, H Takizawa, H Kobayashi 2014 International 3D Systems Integration Conference (3DIC), 1-6, 2014 | 1 | 2014 |
| A capacity-aware thread scheduling method combined with cache partitioning to reduce inter-thread cache conflicts M Sato, R Egawa, H Takizawa, H Kobayashi IEICE TRANSACTIONS on Information and Systems 96 (9), 2047-2054, 2013 | 1 | 2013 |
| A majority-based control scheme for way-adaptable caches M Sato, R Egawa, H Takizawa, H Kobayashi Facing the multicore-challenge, 16-28, 2010 | 1 | 2010 |
| An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems M Sato, T Toyoshima, H Takayashiki, R Egawa, H Kobayashi Supercomputing Frontiers and Innovations 6 (4), 4-19, 2020 | | 2020 |
| A Hardware Prefetching Mechanism for Vector Gather Instructions H Takayashiki, M Sato, K Komatsu, H Kobayashi 2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and …, 2019 | | 2019 |
| A Skewed Multi-banked Cache for Many-core Vector Processors H Takayashiki, M Sato, K Komatsu, H Kobayashi Supercomputing Frontiers and Innovations 6 (3), 86-101, 2019 | | 2019 |
Takizawa HiroyukiTohoku University確認したメール アドレス: tohoku.ac.jp
