Masayuki Sato
Masayuki Sato
確認したメール アドレス: tohoku.ac.jp
タイトル
引用先
引用先
Performance evaluation of a vector supercomputer SX-Aurora TSUBASA
K Komatsu, S Momose, Y Isobe, O Watanabe, A Musa, M Yokokawa, ...
SC18: International Conference for High Performance Computing, Networking …, 2018
342018
A study on measurement of light tar content in the fuel gas produced in small-scale gasification and power generation systems for solid wastes
YI Son, M Sato, T Namioka, K YOSIKAWA
Journal of Environment and Engineering 4 (1), 12-23, 2009
192009
Practical method of gravimetric tar analysis that takes into account a thermal cracking reaction scheme
T Namioka, Y Son, M Sato, K Yoshikawa
Energy & fuels 23 (12), 6156-6162, 2009
162009
A cache-aware thread scheduling policy for multi-core processors
M Sato, I Kotera, R Egawa, H Takizawa, H Kobayashi
Proceedings of the IASTED International Conference on Parallel and …, 2009
112009
A voting-based working set assessment scheme for dynamic cache resizing mechanisms
M Sato, R Egawa, H Takizawa, H Kobayashi
2010 IEEE International Conference on Computer Design, 98-105, 2010
82010
An adaptive demotion policy for high-associativity caches
J Tada, M Sato, R Egawa
Proceedings of the 8th International Symposium on Highly Efficient …, 2017
72017
Search space reduction for parameter tuning of a tsunami simulation on the intel knights landing processor
K Komatsu, T Kishitani, M Sato, A Musa, H Kobayashi
2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018
32018
Vertically integrated processor and memory module design for vector supercomputers
R Egawa, M Sato, J Tada, H Kobayashi
2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013
32013
A flexible insertion policy for dynamic cache resizing mechanisms
M Sato, Y Tobo, R Egawa, H Takizawa, H Kobayashi
2013 IEEE COOL Chips XVI, 1-3, 2013
32013
Optimizing memory layout of hyperplane ordering for vector supercomputer sx-aurora tsubasa
O Watanabe, Y Hougi, K Komatsu, M Sato, A Musa, H Kobayashi
2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC …, 2019
22019
Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA
A Musa, T Abe, T Kishitani, T Inoue, M Sato, K Komatsu, Y Murashima, ...
International Conference on Computational Science, 363-376, 2019
22019
An adjacent-line-merging writeback scheme for stt-ram-based last-level caches
M Sato, Y Shoji, Z Sakai, R Egawa, H Kobayashi
IEEE Transactions on Multi-Scale Computing Systems 4 (4), 593-604, 2018
22018
A cache partitioning mechanism to protect shared data for CMPs
M Sato, S Nishimura, R Egawa, H Takizawa, H Kobayashi
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-2, 2016
22016
Effect of retransmissions in mobile agent communications under unstable network conditions
M Sato, M Urakami, H Matsuno
7th International Conference on Mobile Data Management (MDM'06), 132-132, 2006
22006
An energy-aware set-level refreshing mechanism for eDRAM last-level caches
M Sato, Z Li, R Egawa, H Kobayashi
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2018
12018
An adjacent-line-merging writeback scheme for STT-RAM last-level caches
M Sato, Z Sakai, R Egawa, H Kobayashi
2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-2, 2017
12017
An application-adaptive data allocation method for multi-channel memory
T Toyoshima, M Sato, R Egawa, H Kobayashi
2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2017
12017
An energy-efficient dynamic memory address mapping mechanism
M Sato, C Han, K Komatsu, R Egawa, H Takizawa, H Kobayashi
2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII), 1-3, 2015
12015
On-chip checkpointing with 3D-stacked memories
M Sato, R Egawa, H Takizawa, H Kobayashi
2014 International 3D Systems Integration Conference (3DIC), 1-6, 2014
12014
A capacity-aware thread scheduling method combined with cache partitioning to reduce inter-thread cache conflicts
M Sato, R Egawa, H Takizawa, H Kobayashi
IEICE TRANSACTIONS on Information and Systems 96 (9), 2047-2054, 2013
12013
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