| Performance evaluation of a vector supercomputer SX-Aurora TSUBASA K Komatsu, S Momose, Y Isobe, O Watanabe, A Musa, M Yokokawa, ... SC18: International Conference for High Performance Computing, Networking …, 2018 | 118 | 2018 |
| Performance and power analysis of a vector computing system K Komatsu, A Onodera, E Focht, S Fujimoto, Y Isobe, S Momose, M Sato, ... Supercomputing Frontiers and Innovations 8 (2), 75-94, 2021 | 15 | 2021 |
| An external definition of the one-hot constraint and fast QUBO generation for high-performance combinatorial clustering M Kumagai, K Komatsu, F Takano, T Araki, M Sato, H Kobayashi International Journal of Networking and Computing 11 (2), 463-491, 2021 | 14 | 2021 |
| Optimization of the himeno benchmark for SX-Aurora TSUBASA A Onodera, K Komatsu, S Fujimoto, Y Isobe, M Sato, H Kobayashi Benchmarking, Measuring, and Optimizing: Third BenchCouncil International …, 2021 | 12 | 2021 |
| A cache-aware thread scheduling policy for multi-core processors M Sato, I Kotera, R Egawa, H Takizawa, H Kobayashi Proceedings of the IASTED International Conference on Parallel and …, 2009 | 12 | 2009 |
| Combinatorial clustering based on an externally-defined one-hot constraint M Kumagai, K Komatsu, F Takano, T Araki, M Sato, H Kobayashi 2020 Eighth International Symposium on Computing and Networking (CANDAR), 59-68, 2020 | 8 | 2020 |
| Optimizing memory layout of hyperplane ordering for vector supercomputer SX-Aurora TSUBASA O Watanabe, Y Hougi, K Komatsu, M Sato, A Musa, H Kobayashi 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC …, 2019 | 8 | 2019 |
| A layer-adaptable cache hierarchy by a multiple-layer bypass mechanism R Egawa, R Saito, M Sato, H Kobayashi Proceedings of the 10th International Symposium on Highly-Efficient …, 2019 | 8 | 2019 |
| A voting-based working set assessment scheme for dynamic cache resizing mechanisms M Sato, R Egawa, H Takizawa, H Kobayashi 2010 IEEE International Conference on Computer Design, 98-105, 2010 | 8 | 2010 |
| An adaptive demotion policy for high-associativity caches J Tada, M Sato, R Egawa Proceedings of the 8th International Symposium on Highly Efficient …, 2017 | 7 | 2017 |
| Vertically integrated processor and memory module design for vector supercomputers R Egawa, M Sato, J Tada, H Kobayashi 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013 | 6 | 2013 |
| Detection of machinery failure signs from big time-series data obtained by flow simulation of intermediate-pressure steam turbines K Komatsu, H Miyazawa, C Yiran, M Sato, T Furusawa, S Yamamoto, ... Journal of Engineering for Gas Turbines and Power 144 (1), 011007, 2022 | 5 | 2022 |
| Search space reduction for parameter tuning of a tsunami simulation on the intel knights landing processor K Komatsu, T Kishitani, M Sato, A Musa, H Kobayashi 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018 | 5 | 2018 |
| An appropriate computing system and its system parameters selection based on bottleneck prediction of applications K Komatsu, T Kishitani, M Sato, H Kobayashi 2019 IEEE International Parallel and Distributed Processing Symposium …, 2019 | 4 | 2019 |
| Performance evaluation of tsunami inundation simulation on SX-Aurora TSUBASA A Musa, T Abe, T Kishitani, T Inoue, M Sato, K Komatsu, Y Murashima, ... Computational Science–ICCS 2019: 19th International Conference, Faro …, 2019 | 4 | 2019 |
| An externally-constrained Ising clustering method for material informatics K Komatsu, M Kumagai, J Qi, M Sato, H Kobayashi 2021 Ninth International Symposium on Computing and Networking Workshops …, 2021 | 3 | 2021 |
| A hardware prefetching mechanism for vector gather instructions H Takayashiki, M Sato, K Komatsu, H Kobayashi 2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and …, 2019 | 3 | 2019 |
| An energy-aware set-level refreshing mechanism for eDRAM last-level caches M Sato, Z Li, R Egawa, H Kobayashi 2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2018 | 3 | 2018 |
| An adjacent-line-merging writeback scheme for stt-ram-based last-level caches M Sato, Y Shoji, Z Sakai, R Egawa, H Kobayashi IEEE Transactions on Multi-Scale Computing Systems 4 (4), 593-604, 2018 | 3 | 2018 |
| A cache partitioning mechanism to protect shared data for CMPs M Sato, S Nishimura, R Egawa, H Takizawa, H Kobayashi 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-2, 2016 | 3 | 2016 |
Hiroaki KobayashiTohoku University確認したメール アドレス: tohoku.ac.jp
