フォロー
Masayuki Sato
Masayuki Sato
確認したメール アドレス: tohoku.ac.jp
タイトル
引用先
引用先
Performance evaluation of a vector supercomputer SX-Aurora TSUBASA
K Komatsu, S Momose, Y Isobe, O Watanabe, A Musa, M Yokokawa, ...
SC18: International Conference for High Performance Computing, Networking …, 2018
902018
A cache-aware thread scheduling policy for multi-core processors
M Sato, I Kotera, R Egawa, H Takizawa, H Kobayashi
Proceedings of the IASTED International Conference on Parallel and …, 2009
112009
Optimization of the himeno benchmark for SX-Aurora TSUBASA
A Onodera, K Komatsu, S Fujimoto, Y Isobe, M Sato, H Kobayashi
International Symposium on Benchmarking, Measuring and Optimization, 127-143, 2020
82020
A voting-based working set assessment scheme for dynamic cache resizing mechanisms
M Sato, R Egawa, H Takizawa, H Kobayashi
2010 IEEE International Conference on Computer Design, 98-105, 2010
82010
An adaptive demotion policy for high-associativity caches
J Tada, M Sato, R Egawa
Proceedings of the 8th International Symposium on Highly Efficient …, 2017
72017
Optimizing memory layout of hyperplane ordering for vector supercomputer SX-Aurora TSUBASA
O Watanabe, Y Hougi, K Komatsu, M Sato, A Musa, H Kobayashi
2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC …, 2019
62019
An external definition of the one-hot constraint and fast qubo generation for high-performance combinatorial clustering
M Kumagai, K Komatsu, F Takano, T Araki, M Sato, H Kobayashi
International Journal of Networking and Computing 11 (2), 463-491, 2021
52021
An appropriate computing system and its system parameters selection based on bottleneck prediction of applications
K Komatsu, T Kishitani, M Sato, H Kobayashi
2019 IEEE International Parallel and Distributed Processing Symposium …, 2019
52019
Search space reduction for parameter tuning of a tsunami simulation on the intel knights landing processor
K Komatsu, T Kishitani, M Sato, A Musa, H Kobayashi
2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018
52018
Vertically integrated processor and memory module design for vector supercomputers
R Egawa, M Sato, J Tada, H Kobayashi
2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013
52013
Performance and power analysis of a vector computing system
K Komatsu, A Onodera, E Focht, S Fujimoto, Y Isobe, S Momose, M Sato, ...
Supercomputing Frontiers and Innovations 8 (2), 75-94, 2021
42021
Combinatorial Clustering Based on an Externally-Defined One-Hot Constraint
M Kumagai, K Komatsu, F Takano, T Araki, M Sato, H Kobayashi
2020 Eighth International Symposium on Computing and Networking (CANDAR), 59-68, 2020
32020
Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA
A Musa, T Abe, T Kishitani, T Inoue, M Sato, K Komatsu, Y Murashima, ...
International Conference on Computational Science, 363-376, 2019
32019
An energy-efficient dynamic memory address mapping mechanism
M Sato, C Han, K Komatsu, R Egawa, H Takizawa, H Kobayashi
2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII), 1-3, 2015
32015
A flexible insertion policy for dynamic cache resizing mechanisms
M Sato, Y Tobo, R Egawa, H Takizawa, H Kobayashi
2013 IEEE COOL Chips XVI, 1-3, 2013
32013
Importance of selecting data layouts in the tsunami simulation code
T Kishitani, K Komatsu, M Sato, A Musa, H Kobayashi
2020 IEEE International Parallel and Distributed Processing Symposium …, 2020
22020
A layer-adaptable cache hierarchy by a multiple-layer bypass mechanism
R Egawa, R Saito, M Sato, H Kobayashi
Proceedings of the 10th International Symposium on Highly-Efficient …, 2019
22019
An energy-aware set-level refreshing mechanism for eDRAM last-level caches
M Sato, Z Li, R Egawa, H Kobayashi
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2018
22018
An adjacent-line-merging writeback scheme for stt-ram-based last-level caches
M Sato, Y Shoji, Z Sakai, R Egawa, H Kobayashi
IEEE Transactions on Multi-Scale Computing Systems 4 (4), 593-604, 2018
22018
A cache partitioning mechanism to protect shared data for CMPs
M Sato, S Nishimura, R Egawa, H Takizawa, H Kobayashi
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-2, 2016
22016
現在システムで処理を実行できません。しばらくしてからもう一度お試しください。
論文 1–20