| Asymmetry-aware work-stealing runtimes C Torng, M Wang, C Batten ACM SIGARCH Computer Architecture News 44 (3), 40-52, 2016 | 36 | 2016 |
| Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawaj, C Batten Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 14 | 2017 |
| Efficiently supporting dynamic task parallelism on heterogeneous cache-coherent systems M Wang, T Ta, L Cheng, C Batten 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 10 | 2020 |
| Power‐aware hiding method for S‐box protection J Ma, X Li, M Wang Electronics Letters 50 (22), 1604-1606, 2014 | 8 | 2014 |
| Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. C Torng, M Wang, B Sudheendra, N Murali, S Jayasuriya, S Srinath, ... Hot Chips Symposium, 1, 2016 | 3 | 2016 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
| Efficient Fine-Grain Cooperative Execution of Dynamic Task Parallelism on Heterogeneous Multi/Manycore Systems M Wang Cornell University, 2021 | | 2021 |
| Using Intra-Core Loop-Task Accelerators to Improve the Productivity and Performance of Task-Based Parallel Programs JKSJC Torng, M Wang, SSBIK Al, HC Batten | | 2017 |
