| A low-power and area-efficient design of a weighted pseudorandom test-pattern generator for a test-per-scan built-in self-test architecture V Shivakumar, C Senthilpari, Z Yusoff IEEE Access 9, 29366-29379, 2021 | 17 | 2021 |
| Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs V Shivakumar, C Senthilpari, Z Yusoff Microelectronics Journal 124, 105430, 2022 | 3 | 2022 |
| Design of a 1.9 GHz low-power LFSR circuit using the Reed-Solomon algorithm for Pseudo-Random Test Pattern Generation V Shivakumar, C Senthilpari, Z Yusoff International Journal of Integrated Engineering 13 (6), 220-232, 2021 | 2 | 2021 |
| Storing and retaining divider using BDD-based adder/subtractor circuit SC Pari, D Sigamani, V Priya, RD Kumari International Journal of Computing and Digital Systems 14 (1), 1-xx, 2023 | | 2023 |
| DCVS design and analysis of the LFSR using feedback polynomial function for its low-power and reduced area overhead V Shivakumar, C Senthilpari, Z Yusoff Solid State Technology 63 (4), 7219-7229, 2020 | | 2020 |
Dr.C.SenthilpariSenior Lecturer, Multimedia University, Cyberjaya CampusVerified email at mmu.edu.my
