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Yuanlong Xiao
Yuanlong Xiao
Verified email at alumni.upenn.edu - Homepage
Title
Cited by
Cited by
Year
Reducing FPGA compile time with separate compilation for FPGA building blocks
Y Xiao, D Park, A Butt, H Giesen, Z Han, R Ding, N Magnezi, R Rubin, ...
2019 International Conference on Field-Programmable Technology (ICFPT), 153-161, 2019
312019
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development
Y Xiao, E Micallef, A Butt, M Hofmann, M Alston, M Goldsmith, ...
Proceedings of the 27th ACM International Conference on Architectural …, 2022
222022
Case for fast FPGA compilation using partial reconfiguration
D Park, Y Xiao, N Magnezi, A DeHon
2018 28th International Conference on Field Programmable Logic and …, 2018
192018
Fast linking of separately-compiled FPGA blocks without a NoC
Y Xiao, ST Ahmed, A DeHon
2020 International Conference on Field-Programmable Technology (ICFPT), 196-205, 2020
172020
Fast and flexible FPGA development using hierarchical partial reconfiguration
D Park, Y Xiao, A DeHon
2022 International Conference on Field-Programmable Technology (ICFPT), 1-10, 2022
112022
HiPR: High-level partial reconfiguration for fast incremental FPGA compilation
Y Xiao, A Hota, D Park, A DeHon
2022 32nd International Conference on Field-Programmable Logic and …, 2022
92022
An automatic transistor-level tool for GRM FPGA interconnect circuits optimization
Z Li, Y Xiao, Y Zhang, Y Pang, C Hu, J Wang, J Lai
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 93-98, 2019
62019
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration
L Guo, P Maidee, Y Zhou, C Lavin, E Hung, W Li, J Lau, W Qiao, Y Chi, ...
ACM Transactions on Reconfigurable Technology and Systems 16 (4), 1-30, 2023
32023
HiPR: Fast, incremental custom partial reconfiguration for HLS developers
Y Xiao, A DeHon
Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022
22022
HLS-Compatible, Embedded-Processor Stream Links
E Micallef, Y Xiao, A DeHon
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021
12021
A universal automatic on-chip measurement of FPGA’s internal setup and hold times
Y Xiao, J Wang, J Lai
IEICE Electronics Express 13 (23), 20160810-20160810, 2016
12016
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation
Y Xiao, D Park, ZJ Niu, A Hota, A Dehon
ACM Transactions on Reconfigurable Technology and Systems 17 (2), 1-28, 2024
2024
Asymmetry in Butterfly Fat Tree FPGA NoC
D Park, Z Yao, Y Xiao, A DeHon
2023 International Conference on Field Programmable Technology (ICFPT), 227-231, 2023
2023
Accelerating FPGA Developments from C to Bitstreams by Partial Reconfiguration
Y Xiao
University of Pennsylvania, 2023
2023
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation
A DeHon, H Giesen, N Sultana, Y Xiao
arXiv preprint arXiv:2104.01929, 2021
2021
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits
Z Li, Y Xiao, Y Zhang, Y Pang, J Wang, J Lai
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
2019
A power efficient current-mode differential driver for FPGAs
Y Xiao, J Wang, J Lai
2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, 2015
2015
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