Kentaro Yoshioka
Kentaro Yoshioka
ex. Stanford
Verified email at iskr.elec.keio.ac.jp
Title
Cited by
Cited by
Year
A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS
A Shikata, R Sekimoto, T Kuroda, H Ishikuro
Solid-State Circuits, IEEE Journal of 47 (4), 1022-1030, 2012
1722012
A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS
R Sekimoto, A Shikata, K Yoshioka, T Kuroda, H Ishikuro
IEEE Journal of Solid-State Circuits 48 (11), 2628-2636, 2013
352013
An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS
K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 356-368, 2014
212014
A 40nm 50S/s–8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator
R Sekimoto, A Shikata, T Kuroda, H Ishikuro
ESSCIRC (ESSCIRC), 2011 Proceedings of the, 471-474, 2011
212011
28.7 A 0.7 V 12b 160MS/s 12.8 fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique
K Yoshioka, T Sugimoto, N Waki, S Kim, D Kurose, H Ishii, M Furuta, A Sai, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 478-479, 2017
202017
A 13b SAR ADC with eye-opening VCO based comparator
K Yoshioka, H Ishikuro
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 411-414, 2014
192014
Dynamic architecture and frequency scaling in 0.8–1.2 GS/s 7 b subranging ADC
K Yoshioka, R Saito, T Danjo, S Tsukamoto, H Ishikuro
IEEE Journal of Solid-State Circuits 50 (4), 932-945, 2015
18*2015
An 8bit 0.35–0.8 V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator
K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
2012 Proceedings of the ESSCIRC (ESSCIRC), 381-384, 2012
162012
A power scalable SAR-ADC in 0.18 µm-CMOS with 0.5 V nano-watt operation
R Sekimoto, A Shikata, H Ishikuro
Access Spaces (ISAS), 2011 1st International Symposium on, 89-94, 2011
162011
A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique
K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
2013 Symposium on VLSI Circuits, C266-C267, 2013
132013
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 24096 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC
K Yoshioka, H Kubota, T Fukushima, S Kondo, TT Ta, H Okuni, ...
IEEE Journal of Solid-State Circuits 53 (11), 3026-3038, 2018
10*2018
0.5 V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
M Nomura, A Muramatsu, H Takeno, S Hattori, D Ogawa, M Nasu, ...
2013 Symposium on VLSI Technology, C36-C37, 2013
82013
A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller
A Shikata, R Sekimoto, K Yoshioka, T Kuroda, H Ishikuro
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013
72013
An 802.11 ax 4× 4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer
S Kawai, H Aoyama, R Ito, Y Shimizu, M Ashida, A Maki, T Takeuchi, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 442-444, 2018
6*2018
A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating
R Sekimoto, A Shikata, K Yoshioka, T Kuroda, H Ishikuro
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 161-164, 2012
52012
Amplifier circuit, ad converter, wireless communication device, and sensor system
K Yoshioka, M Furuta, J Matsuno, T Itakura
US Patent 9,577,659, 2017
42017
A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration
K Tanaka, R Saito, H Ishikuro
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
42015
PhaseMAC: A 14 TOPS/W 8bit GRO based phase domain MAC circuit for in-sensor-computed deep learning accelerators
K Yoshioka, Y Toyama, K Ban, D Yashima, S Maya, A Sai, K Onizuka
2018 IEEE Symposium on VLSI Circuits, 263-264, 2018
22018
A voltage scaling 0.25–1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier
K Yoshioka, Y Toyama, T Jyo, H Ishikuro
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 809-812, 2013
22013
A 12.4 TOPS/W, 20% less gate count bidirectional phase domain MAC circuit for DNN inference applications
Y Toyama, K Yoshioka, K Ban, A Sai, K Onizuka
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2018
12018
The system can't perform the operation now. Try again later.
Articles 1–20