| Artificial intelligence for diagnosis and Gleason grading of prostate cancer: the PANDA challenge W Bulten, K Kartasalo, PHC Chen, P Ström, H Pinckaers, K Nagpal, Y Cai, ... Nature medicine 28 (1), 154-163, 2022 | 257 | 2022 |
| A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS A Shikata, R Sekimoto, T Kuroda, H Ishikuro Solid-State Circuits, IEEE Journal of 47 (4), 1022-1030, 2012 | 217 | 2012 |
| Measurement of serum hepcidin-25 levels as a potential test for diagnosing hemochromatosis and related disorders Y Kaneko, H Miyajima, A Piperno, N Tomosugi, H Hayashi, N Morotomi, ... Journal of gastroenterology 45, 1163-1171, 2010 | 63 | 2010 |
| A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 24096 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC K Yoshioka, H Kubota, T Fukushima, S Kondo, TT Ta, H Okuni, ... IEEE Journal of Solid-State Circuits 53 (11), 3026-3038, 2018 | 61 | 2018 |
| A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS R Sekimoto, A Shikata, K Yoshioka, T Kuroda, H Ishikuro IEEE Journal of Solid-State Circuits 48 (11), 2628-2636, 2013 | 47 | 2013 |
| 28.7 A 0.7 V 12b 160MS/s 12.8 fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique K Yoshioka, T Sugimoto, N Waki, S Kim, D Kurose, H Ishii, M Furuta, A Sai, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 478-479, 2017 | 46 | 2017 |
| A 13b SAR ADC with eye-opening VCO based comparator K Yoshioka, H Ishikuro ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 411-414, 2014 | 38 | 2014 |
| An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 356-368, 2014 | 37 | 2014 |
| An 8 bit 12.4 TOPS/W phase-domain MAC circuit for energy-constrained deep learning accelerators Y Toyama, K Yoshioka, K Ban, S Maya, A Sai, K Onizuka IEEE Journal of Solid-State Circuits 54 (10), 2730-2742, 2019 | 26 | 2019 |
| An 802.11 ax 4× 4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer S Kawai, H Aoyama, R Ito, Y Shimizu, M Ashida, A Maki, T Takeuchi, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 442-444, 2018 | 24* | 2018 |
| An 8bit 0.35–0.8 V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro 2012 Proceedings of the ESSCIRC (ESSCIRC), 381-384, 2012 | 23 | 2012 |
| A 40nm 50S/s–8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator R Sekimoto, A Shikata, T Kuroda, H Ishikuro ESSCIRC (ESSCIRC), 2011 Proceedings of the, 471-474, 2011 | 22 | 2011 |
| The PANDA challenge: Prostate cANcer graDe Assessment using the Gleason grading system W Bulten, G Litjens, H Pinckaers, P Ström, M Eklund, K Kartasalo, ... MICCAI challenge, 2020 | 20 | 2020 |
| A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique K Yoshioka, H Kubota, T Fukushima, S Kondo, TT Ta, H Okuni, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 92-94, 2018 | 19 | 2018 |
| A power scalable SAR-ADC in 0.18 µm-CMOS with 0.5 V nano-watt operation R Sekimoto, A Shikata, H Ishikuro Access Spaces (ISAS), 2011 1st International Symposium on, 89-94, 2011 | 18 | 2011 |
| 5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE S Kondo, H Kubota, H Katagiri, Y Ota, M Hirono, TT Ta, H Okuni, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 94-96, 2020 | 17 | 2020 |
| An 802.11 ax 4× 4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer S Kawai, H Aoyama, R Ito, Y Shimizu, M Ashida, A Maki, T Takeuchi, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 442-444, 2018 | 17 | 2018 |
| An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE S Kondo, H Kubota, H Katagiri, Y Ota, M Hirono, TT Ta, H Okuni, ... IEEE Journal of Solid-State Circuits 55 (11), 2866-2877, 2020 | 16 | 2020 |
| Dynamic architecture and frequency scaling in 0.8–1.2 GS/s 7 b subranging ADC K Yoshioka, R Saito, T Danjo, S Tsukamoto, H Ishikuro IEEE Journal of Solid-State Circuits 50 (4), 932-945, 2015 | 16 | 2015 |
| A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique K Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro 2013 Symposium on VLSI Circuits, C266-C267, 2013 | 16 | 2013 |
Tadahiro KurodaProfessor of EECS, The University of TokyoVerified email at g.ecc.u-tokyo.ac.jp
