フォロー
Timothy J Purcell
Timothy J Purcell
Architect
確認したメール アドレス: nvidia.com - ホームページ
タイトル
引用先
引用先
A Survey of General‐Purpose Computation on Graphics Hardware
JD Owens, D Luebke, N Govindaraju, M Harris, J Krüger, AE Lefohn, ...
Computer graphics forum 26 (1), 80-113, 2007
32552007
Ray tracing on programmable graphics hardware
TJ Purcell, I Buck, WR Mark, P Hanrahan
ACM Transactions on Graphics (TOG) 21 (3), 703-712, 2002
10442002
Photon mapping on programmable graphics hardware
TJ Purcell, C Donner, M Cammarano, HW Jensen, P Hanrahan
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware …, 2003
5642003
Realtime ray tracing and its use for interactive global illumination
I Wald, TJ Purcell, J Schmittler, C Benthin, P Slusallek
Eurographics State of the Art Reports 1 (3), 5, 2003
1442003
Ray tracing on a stream processor
TJ Purcell
stanford university, 2004
1332004
A toolkit for computation on GPUs
I Buck, T Purcell
GPU Gems, 621-636, 2004
852004
Efficient memory virtualization in multi-threaded processing units
N Barrow-williams, B Fahs, JF Duluk Jr, JL Deming, TJ Purcell, L Dunning, ...
US Patent 10,037,228, 2018
452018
Defect pinning in monolayer films by highly controlled graphite defects: Molecule corrals
DL Patrick, VJ Cee, TJ Purcell, TP Beebe
Langmuir 12 (7), 1830-1835, 1996
281996
Order-preserving distributed rasterizer
SE Molnar, EM Kilgariff, JS Rhoades, TJ Purcell, SJ Treichler, ZS Hakura, ...
US Patent 8,587,581, 2013
252013
Scheduling and management of compute tasks with different execution priority levels
TJ Purcell, LV Shah, JF Duluk Jr
US Patent App. 13/236,473, 2013
252013
Hardware-managed virtual buffers using a shared memory for load distribution
EM Kilgariff, SE Molnar, SJ Treichler, JS Rhoades, G Schaufler, ...
US Patent 8,760,460, 2014
222014
Optimizing search strategies in kd trees
N Sample, M Haines, M Arnold, T Purcell
5th WSES/IEEE World Multiconference on Circuits, Systems, Communications …, 2001
22*2001
Rasterization tile coalescer and reorder buffer
TJ Purcell, SE Molnar
US Patent 8,605,102, 2013
202013
Transition from epitaxial to nonepitaxial ordered monolayers in pyrolyzed 8CB studied by STM
F Stevens, DL Patrick, VJ Cee, TJ Purcell, TP Beebe
Langmuir 14 (9), 2396-2401, 1998
201998
Control mechanism for fine-tuned cache to backing-store synchronization
JP Robertson, GA Muthler, H Hossain, TJ Purcell, K Mehra, PB Holmqvist, ...
US Patent 9,639,466, 2017
192017
Automatic dependent task launch
PA Cuadra, LV Shah, TJ Purcell, GF Luiz, JF Duluk Jr
US Patent App. 13/360,581, 2013
152013
Scheduling and execution of compute tasks
KM Abdalla, LV Shah, JF Duluk Jr, TJ Purcell, T Mandal, G Hirota
US Patent App. 13/353,155, 2013
152013
Efficient memory virtualization in multi-threaded processing units
N Barrow-williams, B Fahs, JF Duluk Jr, JL Deming, TJ Purcell, L Dunning, ...
US Patent 10,310,973, 2019
112019
Scheduling and execution of compute tasks
KM Abdalla, LV Shah, JF Duluk Jr, TJ Purcell, T Mandal, G Hirota
US Patent 9,069,609, 2015
102015
Compute work distribution reference counters
PA Cuadra, KM Abdalla, JF Duluk Jr, L Durant, GF Luiz, TJ Purcell, ...
US Patent 9,507,638, 2016
82016
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