| Benchmarking nanotechnology for high-performance and low-power logic transistor applications R Chau, S Datta, M Doczy, B Doyle, B Jin, J Kavalieros, A Majumdar, ... IEEE transactions on nanotechnology 4 (2), 153-158, 2005 | 836 | 2005 |
| High-/spl kappa//metal-gate stack and its MOSFET characteristics R Chau, S Datta, M Doczy, B Doyle, J Kavalieros, M Metz IEEE Electron Device Letters 25 (6), 408-410, 2004 | 681 | 2004 |
| High performance fully-depleted tri-gate CMOS transistors BS Doyle, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, T Linton, ... IEEE Electron Device Letters 24 (4), 263-265, 2003 | 630 | 2003 |
| Two-dimensional gallium nitride realized via graphene encapsulation ZY Al Balushi, K Wang, RK Ghosh, RA Vilá, SM Eichfeld, JD Caldwell, ... Nature materials 15 (11), 1166-1171, 2016 | 500 | 2016 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 6,858,478, 2005 | 480 | 2005 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta US Patent 7,358,121, 2008 | 447 | 2008 |
| Integrated nanoelectronics for the future R Chau, B Doyle, S Datta, J Kavalieros, K Zhang Nature materials 6 (11), 810-812, 2007 | 427 | 2007 |
| Atomically thin resonant tunnel diodes built from synthetic van der Waals heterostructures YC Lin, RK Ghosh, R Addou, N Lu, SM Eichfeld, H Zhu, MY Li, X Peng, ... Nature communications 6 (1), 1-6, 2015 | 366 | 2015 |
| Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout B Doyle, B Boyanov, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003 | 347 | 2003 |
| Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering J Kavalieros, B Doyle, S Datta, G Dewey, M Doczy, B Jin, D Lionberger, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 50-51, 2006 | 316 | 2006 |
| Ferroelectric FET analog synapse for acceleration of deep neural network training M Jerry, PY Chen, J Zhang, P Sharma, K Ni, S Yu, S Datta 2017 IEEE International Electron Devices Meeting (IEDM), 6.2. 1-6.2. 4, 2017 | 292 | 2017 |
| A steep-slope transistor based on abrupt electronic phase transition N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ... Nature communications 6 (1), 1-6, 2015 | 283 | 2015 |
| Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication SA Hareland, RS Chau, BS Doyle, R Rios, T Linton, S Datta US Patent 7,820,513, 2010 | 276 | 2010 |
| Atomic layer deposition of high dielectric constant gate dielectrics M Metz, C Boyd, M Kuhn, S Datta, J Kavalieros, M Doczy, J Brask, R Chau US Patent App. 10/943,693, 2006 | 273 | 2006 |
| Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication SA Hareland, RS Chau, BS Doyle, R Rios, T Linton, S Datta US Patent 7,456,476, 2008 | 264 | 2008 |
| Method and apparatus for improving stability of a 6T CMOS SRAM cell S Datta, BS Doyle, RS Chau, J Kavalieros, B Zheng, SA Hareland US Patent 6,970,373, 2005 | 253 | 2005 |
| CMOS devices with a single work function gate electrode and method of fabrication B Doyle, BY Jin, J Kavalieros, S Datta, J Brask, R Chau US Patent App. 11/238,447, 2007 | 247 | 2007 |
| Temperature-Dependent–Characteristics of a VerticalTunnel FET S Mookerjea, D Mohata, T Mayer, V Narayanan, S Datta IEEE Electron Device Letters 31 (6), 564-566, 2010 | 236 | 2010 |
| SRAM and logic transistors with variable height multi-gate transistor architecture S Datta, BS Doyle, JT Kavalieros, Y Wang US Patent App. 11/648,521, 2008 | 235 | 2008 |
| The era of hyper-scaling in electronics S Salahuddin, K Ni, S Datta Nature Electronics 1 (8), 442-450, 2018 | 225 | 2018 |
Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State University在 cse.psu.edu 的电子邮件经过验证
