Hayun Chung
Hayun Chung
Assistant Professor of Electronics and Information Engineering, Korea University
Verified email at korea.ac.kr
Title
Cited by
Cited by
Year
50% active-power saving without speed degradation using standby power reduction (SPR) circuit
K Seta, H Hara, T Kuroda, M Kakumu, T Sakurai
Proceedings ISSCC'95-International Solid-State Circuits Conference, 318-319, 1995
184*1995
A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
H Chung, A Rylyakov, ZT Deniz, J Bulzacchelli, GY Wei, D Friedman
2009 Symposium on VLSI Circuits, 268-269, 2009
572009
6W/25mm2 inductive power transfer for non-contact wafer-level testing
A Radecki, H Chung, Y Yoshida, N Miura, T Shidei, H Ishikuro, T Kuroda
2011 IEEE International Solid-State Circuits Conference, 230-232, 2011
532011
A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS
H Chung, H Ishikuro, T Kuroda
IEEE Journal of Solid-State Circuits 47 (5), 1232-1241, 2012
522012
A 0.025–0.45 W 60%-efficiency inductive-coupling power transceiver with 5-bit dual-frequency feedforward control for non-contact memory cards
H Chung, A Radecki, N Miura, H Ishikuro, T Kuroda
IEEE journal of solid-state circuits 47 (10), 2496-2504, 2012
182012
Design-space exploration of backplane receivers with high-speed ADCs and digital equalization
H Chung, GY Wei
2009 IEEE Custom Integrated Circuits Conference, 555-558, 2009
182009
A 0.5 V 10MHz-to-100MHz 0.47 μz power scalable AD-PLL in 40nm CMOS
Y Hiraku, I Hayashi, H Chung, T Kuroda, H Ishikuro
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 33-36, 2012
82012
A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13 μm CMOS
H Chung, A Liu, GY Wei
2008 IEEE Custom Integrated Circuits Conference, 563-566, 2008
72008
25.3 A 1.35 V 5.0 Gb/s/pin GDDR5M with 5.4 mW standby power and an error-adaptive duty-cycle corrector
HW Lee, J Song, SA Hyun, S Baek, Y Lim, J Lee, M Park, H Choi, C Choi, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
62014
ADC-based backplane receiver design-space exploration
H Chung, GY Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (7 …, 2013
42013
A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
H Chung, ZT Deniz, A Rylyakov, J Bulzacchelli, D Friedman, GY Wei
Analog Integrated Circuits and Signal Processing 85 (2), 299-310, 2015
22015
6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing
A Radecki, H Chung, Y Yoshida, N Miura, T Shidei, H Ishikuro, T Kuroda
IEICE transactions on electronics 95 (4), 668-676, 2012
22012
Simultaneous data and power transmission using nested clover coils
Y Take, H Chung, N Miura, T Kuroda
17th Asia and South Pacific Design Automation Conference, 555-556, 2012
12012
Inductive-coupling interfaces for high-speed low-power proximity communications
H Chung, T Kuroda
2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011
12011
ADC-Based Backplane Receivers
H Chung
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 16 (3), 300-311, 2016
2016
Non-linear MLE-based digital equaliser for ADC-based backplane receivers
H Chung
Electronics Letters 52 (13), 1106-1108, 2016
2016
Simulated-annealing-based adaptive equaliser for on-die variation compensation
H Chung, GY Wei
Electronics letters 48 (1), 18-19, 2012
2012
Design considerations for ADC-based backplane receivers
H Chung, GY Wei
2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011
2011
Design considerations for high-speed backplane transceivers with digital adaptive equalizers
HC Chung
Harvard University, 2009
2009
ISSCC 2011/SESSION 12/DESIGN IN EMERGING TECHNOLOGIES/12.8
A Radecki, H Chung, Y Yoshida, N Miura, T Shidei, H Ishikuro, T Kuroda
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Articles 1–20