| A lightweight fault-tolerant mechanism for network-on-chip M Koibuchi, H Matsutani, H Amano, TM Pinkston Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 13-22, 2008 | 166 | 2008 |
| A case for random shortcut topologies for HPC interconnects M Koibuchi, H Matsutani, H Amano, DF Hsu, H Casanova 2012 39th Annual International Symposium on Computer Architecture (ISCA …, 2012 | 134 | 2012 |
| A scalable 3D heterogeneous multicore with an inductive ThruChip interface N Miura, Y Koizumi, Y Take, H Matsutani, T Kuroda, H Amano, ... IEEE Micro 33 (6), 6-15, 2013 | 113 | 2013 |
| Run-time power gating of on-chip routers using look-ahead routing H Matsutani, M Koibuchi, H Amano, D Wang 2008 Asia and South Pacific Design Automation Conference, 55-60, 2008 | 113 | 2008 |
| Prediction router: Yet another low latency on-chip router architecture H Matsutani, M Koibuchi, H Amano, T Yoshinaga 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 110 | 2009 |
| Tightly-coupled multi-layer topologies for 3-D NoCs H Matsutani, M Koibuchi, H Amano 2007 International Conference on Parallel Processing (ICPP 2007), 75-75, 2007 | 85 | 2007 |
| Ultra fine-grained run-time power gating of on-chip routers for CMPs H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 61-68, 2010 | 69 | 2010 |
| Adding slow-silent virtual channels for low-power on-chip networks H Matsutani, M Koibuchi, D Wang, H Amano Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 23-32, 2008 | 65 | 2008 |
| 3D NoC with inductive-coupling links for building-block SiPs Y Take, H Matsutani, D Sasaki, M Koibuchi, T Kuroda, H Amano IEEE Transactions on Computers 63 (3), 748-763, 2012 | 62 | 2012 |
| Low-latency wireless 3D NoCs via randomized shortcut chips H Matsutani, M Koibuchi, I Fujiwara, T Kagami, Y Take, T Kuroda, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 47 | 2014 |
| A case for wireless 3D NoCs for CMPs H Matsutani, P Bogdan, R Marculescu, Y Take, D Sasaki, H Zhang, ... 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 23-28, 2013 | 44 | 2013 |
| Performance, cost, and energy evaluation of fat h-tree: A cost-efficient tree-based on-chip network H Matsutani, M Koibuchi, H Amano 2007 IEEE International Parallel and Distributed Processing Symposium, 1-10, 2007 | 43 | 2007 |
| Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 42 | 2011 |
| Layout-conscious random topologies for HPC off-chip interconnects M Koibuchi, I Fujiwara, H Matsutani, H Casanova 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 40 | 2013 |
| The dependable responsive multithreaded processor for distributed real-time systems K Suito, R Ueda, K Fujii, T Kogo, H Matsutani, N Yamasaki IEEE Micro 32 (6), 52-61, 2012 | 39 | 2012 |
| Prediction router: A low-latency on-chip router architecture with multiple predictors H Matsutani, M Koibuchi, H Amano, T Yoshinaga IEEE Transactions on Computers 60 (6), 783-799, 2011 | 33 | 2011 |
| MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link S Saito, Y Kohama, Y Sugimori, Y Hasegawa, H Matsutani, T Sano, ... 2009 International Conference on Field Programmable Logic and Applications, 6-11, 2009 | 33 | 2009 |
| Fat H-Tree: A cost-efficient tree-based on-chip network H Matsutani, M Koibuchi, Y Yamada, DF Hsu, H Amano IEEE Transactions on Parallel and Distributed Systems 20 (8), 1126-1141, 2008 | 33 | 2008 |
| An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor Y Hasegawa, S Abe, H Matsutani, H Amano, K Anjo, T Awashima Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005 | 28 | 2005 |
| A vertical bubble flow network using inductive-coupling for 3-D CMPs H Matsutani, Y Take, D Sasaki, M Kimura, Y Ono, Y Nishiyama, ... Proceedings of the Fifth ACM/IEEE International Symposium, 49-56, 2011 | 26 | 2011 |
