Follow
Ckristian Duran
Ckristian Duran
Universidad Industrial de Santander, The University of Electro-Communications
Verified email at correo.uis.edu.co
Title
Cited by
Cited by
Year
A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC
C Duran, DL Rueda, G Castillo, A Agudelo, C Rojas, L Chaparro, ...
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 315-318, 2016
142016
Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage
H Gomez, C Duran, E Roa
IEEE Transactions on Consumer Electronics 65 (1), 109-118, 2019
102019
A system-on-chip platform for the Internet of Things featuring a 32-bit RISC-V based microcontroller
C Duran, A Amaya, R Torres, J Ardila, L Rueda, G Castillo, A Agudelo, ...
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017
102017
An energy-efficient RISC-V RV32IMAC microcontroller for periodical-driven sensing applications
C Duran, M Wachs, A Huntington, J Ardila, J Kang, A Amaya, H Gomez, ...
2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020
92020
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse
R Serrano, C Duran, TT Hoang, M Sarmiento, KD Nguyen, A Tsukamoto, ...
IEEE Access 9, 105748-105755, 2021
62021
Quick Boot of Trusted Execution Environment With Hardware Accelerators
TT Hoang, C Duran, DT Nguyen-Hoang, DH Le, A Tsukamoto, K Suzaki, ...
IEEE Access 8, 74015-74023, 2020
62020
Standard cell camouflage method to counter silicon reverse engineering
H Gomez, C Duran, E Roa
2018 IEEE International Conference on Consumer Electronics (ICCE), 1-4, 2018
62018
A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller
H Morales, C Duran, E Roa
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 97-100, 2019
52019
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications
M Sarmiento, KD Nguyen, C Duran, TT Hoang, R Serrano, VP Hoang, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (9), 3182-3186, 2021
42021
AES Sbox Acceleration Schemes for Low-Cost SoCs
C Duran, H Gomez, E Roa
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
42021
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)
TT Hoang, C Duran, KD Nguyen, TK Dang, QNQ Nhu, PH Than, XT Tran, ...
IEICE Electronics Express, 17.20200282, 2020
42020
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling
TT Hoang, C Duran, R Serrano, M Sarmiento, KD Nguyen, A Tsukamoto, ...
IEEE Access 10, 46014-46027, 2022
32022
Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors
C Duran, H Morales, C Rojas, A Ruospo, E Sanchez, E Roa
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020
32020
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3
R Serrano, C Duran, TT Hoang, M Sarmiento, A Tsukamoto, K Suzaki, ...
2021 18th International SoC Design Conference (ISOCC), 17-18, 2021
22021
Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors
TT Hoang, C Duran, A Tsukamoto, K Suzaki, CK Pham
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020
22020
Regulación de voltaje por control de disparo empleando tecnologias FPAA
CR Durán-Blanco, JA Flórez-Vargas, R Alzate-Castaño
TecnoLógicas, 2013
22013
A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse
R Serrano, C Duran, M Sarmiento, TT Hoang, A Tsukamoto, K Suzaki, ...
IEEE Access 10, 41852-41862, 2022
12022
A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration
C Duran, E Roa
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 1612-1616, 2021
12021
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications
R Serrano, M Sarmiento, C Duran, KD Nguyen, TT Hoang, K Ishibashi, ...
2021 18th International SoC Design Conference (ISOCC), 375-376, 2021
12021
TEE Boot Procedure with Crypto-accelerators in RISC-V Processors
C Duran, TT Hoang, A Tsukamoto, K Suzaki, CK Pham
Proc. 4th Workshop Comput. Archit. Res.(RISC-V), Virtual Workshop, 2020
12020
The system can't perform the operation now. Try again later.
Articles 1–20