| OpenCL-based FPGA-platform for stencil computation and its optimization methodology HM Waidyasooriya, Y Takei, S Tatsumi, M Hariyama IEEE Transactions on Parallel and Distributed Systems 28 (5), 1390-1402, 2016 | 90 | 2016 |
| A low-power FPGA based on autonomous fine-grain power gating S Ishihara, M Hariyama, M Kameyama IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (8 …, 2010 | 86 | 2010 |
| VLSI processor for reliable stereo matching based on adaptive window-size selection M Hariyama, T Takeuchi, M Kameyama Proceedings 2001 ICRA. IEEE International Conference on Robotics and …, 2001 | 69 | 2001 |
| FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture M Hariyama, Y Kobayashi, H Sasaki, M Kameyama IEICE Transactions on Fundamentals of Electronics, Communications and …, 2005 | 57 | 2005 |
| Design of FPGA-based computing systems with OpenCL HM Waidyasooriya, M Hariyama, K Uchiyama Springer International Publishing, 2018 | 56 | 2018 |
| Hardware-acceleration of short-read alignment based on the burrows-wheeler transform HM Waidyasooriya, M Hariyama IEEE Transactions on Parallel and Distributed Systems 27 (5), 1358-1372, 2015 | 43 | 2015 |
| Evaluation of a field-programmable VLSI based on an asynchronous bit-serial architecture M Hariyama, S Ishihara, M Kameyama IEICE transactions on electronics 91 (9), 1419-1426, 2008 | 36 | 2008 |
| Asynchronous domino logic pipeline design based on constructed critical data path Z Xia, M Hariyama, M Kameyama IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 619-630, 2014 | 34 | 2014 |
| Multi-FPGA accelerator architecture for stencil computation exploiting spacial and temporal scalability HM Waidyasooriya, M Hariyama IEEE Access 7, 53188-53201, 2019 | 33 | 2019 |
| Reliable stereo matching for highly-safe intelligent vehicles and its VLSI implementation M Hariyama, T Takeuchi, M Kameyama Proceedings of the IEEE Intelligent Vehicles Symposium 2000 (Cat. No …, 2000 | 29 | 2000 |
| Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit Z Xia, S Ishihara, M Hariyama, M Kameyama 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 3017-3020, 2012 | 26 | 2012 |
| VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture M Hariyama, M Kameyama 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 26 | 2004 |
| A low-power field-programmable VLSI based on a fine-grained power-gating scheme M Hariyama, S Ishihara, M Kameyama 2008 51st Midwest Symposium on Circuits and Systems, 702-705, 2008 | 25 | 2008 |
| Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure N Ohsawa, O Sakamoto, M Hariyama, M Kameyama IEEE Computer Society Annual Symposium on VLSI, 258-259, 2004 | 24 | 2004 |
| A field-programmable VLSI based on an asynchronous bit-serial architecture M Hariyama, S Ishihara, CC Wei, M Kameyama 2007 IEEE Asian Solid-State Circuits Conference, 380-383, 2007 | 23 | 2007 |
| Architecture of a multi-context FPGA using reconfigurable context memory W Chong, S Ogata, M Hariyama, M Kameyama 19th IEEE International Parallel and Distributed Processing Symposium, 7 pp., 2005 | 22 | 2005 |
| A collision detection processor for intelligent vehicles M Hariyama, M Kameyama IEICE Transactions on Electronics 76 (12), 1804-1811, 1993 | 22 | 1993 |
| Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access M Hariyama, H Sasaki, M Kameyama IEICE transactions on information and systems 88 (7), 1486-1491, 2005 | 21 | 2005 |
| Highly-parallel FPGA accelerator for simulated quantum annealing HM Waidyasooriya, M Hariyama IEEE Transactions on Emerging Topics in Computing 9 (4), 2019 | 20 | 2019 |
| OpenCL-based design of an FPGA accelerator for quantum annealing simulation HM Waidyasooriya, M Hariyama, MJ Miyama, M Ohzeki The Journal of Supercomputing 75, 5019-5039, 2019 | 19 | 2019 |
