| SuperENC: MPEG-2 video encoder chip M Ikeda, T Kondo, K Nitta, K Suguri, T Yoshitome, T Minami, H Iwasaki, ... IEEE Micro 19 (4), 56-65, 1999 | 44 | 1999 |
| Single-chip MPEG-2 422P@ HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level I Iwasaki, J Naganuma, K Nitta, K Nakamura, T Yoshitome, M Ogura, ... 2003 Design, Automation and Test in Europe Conference and Exhibition, 2-7 suppl., 2003 | 39 | 2003 |
| Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability T Onishi, T Sano, Y Nishida, K Yokohari, J Su, K Nakamura, K Nitta, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C54-C55, 2015 | 29 | 2015 |
| An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture M Ikeda, T Kondo, K Nitta, K Suguri, T Yoshitome, T Minami, J Naganuma, ... Proceedings of the conference on Design, automation and test in Europe, 10-es, 1999 | 25 | 1999 |
| An H. 264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures K Nitta, H Iwasaki, T Onishi, T Sano, A Sagata, Y Nakajima, M Inamori, ... IEICE transactions on electronics 95 (4), 432-440, 2012 | 24 | 2012 |
| A single-chip 4K 60-fps 4: 2: 2 HEVC video encoder LSI employing efficient motion estimation and mode decision framework with scalability to 8K T Onishi, T Sano, Y Nishida, K Yokohari, K Nakamura, K Nitta, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018 | 23 | 2018 |
| A single-chip MPEG2 MP@ ML video encoder LSI with multi-chip configuration for a single-board MP@ HL encoder T Minami, T Kondo, K Nitta, K Suguri, M Ikeda, T Yoshitome, H Watanabe, ... Hot Chips 10, 1998 | 23 | 1998 |
| VASA: Single-chip MPEG-2 422P@ HL CODEC LSI with Multi-chip Configuration for Large Scale Processing beyond HDTV Level J Naganuma, H Iwasaki, K Nitta, K Nakamura, T Yoshitome, M Ogura, ... IEEE Hot Chips 14, 2002-8, 2002 | 14 | 2002 |
| Development of an HDTV MPEG-2 encoder based on multiple enhanced SDTV encoding LSIs T Yoshitome, K Nakamura, K Nitta, M Ikeda, M Endo ICCE. International Conference on Consumer Electronics (IEEE Cat. No …, 2001 | 7 | 2001 |
| Motion-estimation/motion-compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG-2 MP@ ML video encoder K Nitta, T Minami, T Kondo, T Ogura Visual Communications and Image Processing'99 3653, 874-882, 1998 | 7 | 1998 |
| Computational power of nondeterministic ordered binary decision diagrams and their subclasses K Takagi, K Nitta, H Bouno, Y Takenaga, S Yajima IEICE transactions on fundamentals of electronics, communications and …, 1997 | 6 | 1997 |
| Low delay 4K 120fps HEVC decoder with parallel processing architecture K Nakamura, D Kobayashi, Y Omori, T Osawa, T Onishi, K Nitta, H Iwasaki IEICE Transactions on Electronics 103 (3), 77-84, 2020 | 5 | 2020 |
| MVC real-time video encoder for full-HDTV 3D video M Ikeda, T Onishi, T Sano, A Sagata, H Iwasaki, Y Nakajima, K Nitta, ... 2012 IEEE International Conference on Consumer Electronics (ICCE), 166-167, 2012 | 5 | 2012 |
| The intermediate service platform architecture for home networking services T Yamazaki, H Inagaki, K Nitta, M Ito IEEE International Symposium on Consumer Electronics (ISCE 2010), 1-6, 2010 | 4 | 2010 |
| Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder K NITTA, T MINAMI, T KONDO, T OGURA IEICE TRANSACTIONS on Information and Systems 84 (3), 317-325, 2001 | 4 | 2001 |
| Professional H. 265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure H Iwasaki, T Onishi, K Nakamura, K Nitta, T Sano, Y Nishida, K Yokohari, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-24, 2015 | 3 | 2015 |
| Motion search apparatus in video coding K Nitta, H Iwasaki, J Naganuma US Patent 8,428,137, 2013 | 3 | 2013 |
| Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H. 264/AVC encoder LSI T Onishi, T Sano, K Nitta, M Ikeda, J Naganuma 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 800-803, 2008 | 3 | 2008 |
| Opencl-based design of an FPGA accelerator for h. 266/vvc transform and quantization HM Waidyasooriya, M Hariyama, H Iwasaki, D Kobayashi, Y Omori, ... 2022 IEEE 65th International Midwest Symposium on Circuits and Systems …, 2022 | 2 | 2022 |
| FPGA-based network microburst analysis system with flow specification and efficient packet capturing S Yoshida, Y Ukon, S Ohteru, H Uzawa, N Ikeda, K Nitta 2020 IEEE 31st International Conference on Application-specific Systems …, 2020 | 2 | 2020 |
Hiroe IWASAKITokyo University of Agriculture and Technology確認したメール アドレス: go.tuat.ac.jp
