| A network on chip architecture and design methodology S Kumar, A Jantsch, JP Soininen, M Forsell, M Millberg, J Oberg, ... Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms …, 2002 | 1688 | 2002 |
| Networks on chip A Jantsch, J Soininen, M Forsell, L Zheng, S Kumar, M Millberg, J Öberg Workshop at the European Solid State Circuits Conference, 2001 | 996 | 2001 |
| Network on chip: An architecture for billion transistor era A Hemani, A Jantsch, S Kumar, A Postula, J Oberg, M Millberg, ... Proceeding of the IEEE NorChip Conference 31 (20), 0, 2000 | 607 | 2000 |
| Load distribution with the proximity congestion awareness in a network on chip E Nilsson, M Millberg, J Oberg, A Jantsch 2003 Design, Automation and Test in Europe Conference and Exhibition, 1126-1127, 2003 | 222 | 2003 |
| Lowering power consumption in clock by using globally asynchronous locally synchronous design style A Hemani, T Meincke, S Kumar, A Postula, T Olsson, P Nilsson, J Oberg, ... Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 873-878, 1999 | 215 | 1999 |
| Hardware/software partitioning and minimizing memory interface traffic A Jantsch, P Ellervee, A Hemani, J Öberg, H Tenhunen European Design Automation Conference: Proceedings of the conference on …, 1994 | 135 | 1994 |
| A case study on hardware/software partitioning A Jantsch, P Ellervee, J Oberg, A Hemani Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 111-118, 1994 | 95 | 1994 |
| Grammar-based hardware synthesis of data communication protocols J OEberg, A Kumar, A Hemani Proceedings of the 9th international symposium on System synthesis, 14, 1996 | 67 | 1996 |
| Toward a scalable test methodology for 2D-mesh network-on-chips K Petersén, J Oberg 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 63 | 2007 |
| Globally asynchronous locally synchronous architecture for large high-performance ASICs T Meincke, A Hemani, S Kumar, P Ellervee, J Oberg, T Olsson, P Nilsson, ... 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 512-515, 1999 | 60 | 1999 |
| Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking E Nilsson, J Öberg Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004 | 57 | 2004 |
| Grammar based modelling and synthesis of device drivers and bus interfaces M O'Nils, J Oberg, A Jantsch Proceedings. 24th EUROMICRO Conference (Cat. No. 98EX204) 1, 55-58, 1998 | 31 | 1998 |
| Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen VLSI-SOC, 362-, 2003 | 30 | 2003 |
| A NoC System generator for the Sea-of-Cores era J Öberg, F Robino FPGAWorld-2011, Proceedings of the 8th FPGAWorld Conference, Stockholm, 2011 …, 2011 | 29 | 2011 |
| Clocking strategies for networks-on-chip J Öberg Networks on chip, 153-172, 2003 | 28 | 2003 |
| System level virtual prototyping of DSP SOCs using grammar based approach A Hemani, AK Deb, J Oberg, A Postula, D Lindqvist, B Fjellborg Design Automation for Embedded Systems 5 (3), 295-311, 2000 | 28 | 2000 |
| Grammar-based hardware synthesis from port-size independent specifications J Oberg, A Kumar, A Hemani IEEE transactions on very large scale integration (VLSI) systems 8 (2), 184-194, 2000 | 27 | 2000 |
| ProGram: A Grammar-Based Method for Specification and Hardware Synthesis of Communication Protocols J Öberg | 22 | 1999 |
| A software oriented approach to hardware/software codesign A Jantsch, P Ellervee, J Oberg, A Hemani, H Tenhunen Proc. of the Poster Session of CC, 1994 | 22 | 1994 |
| A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen Integration 38 (1), 3-17, 2004 | 20 | 2004 |
Axel JantschTU Wien, Vienna, Austria (Vienna University of Technology)Verified email at tuwien.ac.at
