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Chikaaki Kodama
Chikaaki Kodama
KIOXIA Corporation
Verified email at big.or.jp - Homepage
Title
Cited by
Cited by
Year
MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF
K Yanagidaira, C Kodama
US Patent 20,090,155,990, 2009
1542009
Self-aligned double and quadruple patterning-aware grid routing with hotspots control
C Kodama, H Ichikawa, K Nakayama, T Kotani, S Nojima, S Mimotogi, ...
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 267-272, 2013
442013
A machine learning based framework for sub-resolution assist feature generation
X Xu, T Matsunawa, S Nojima, C Kodama, T Kotani, DZ Pan
Proceedings of the 2016 on International Symposium on Physical Design, 161-168, 2016
432016
Selected sequence-pair: An efficient decodable packing representation in linear time using sequence-pair
C Kodama, K Fujiyoshi
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
392003
Self-aligned double and quadruple patterning layout principle
K Nakayama, C Kodama, T Kotani, S Nojima, S Mimotogi, S Miyamoto
Design for Manufacturability through Design-Process Integration VI 8327, 252-260, 2012
362012
Subresolution assist feature generation with supervised data learning
X Xu, Y Lin, M Li, T Matsunawa, S Nojima, C Kodama, T Kotani, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
292017
Improved method of cell placement with symmetry constraints for analog IC layout design
S Kouda, C Kodama, K Fujiyoshi
Proceedings of the 2006 international symposium on Physical design, 192-199, 2006
292006
Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation
Y Tomioka, T Matsunawa, C Kodama, S Nojima
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 81-86, 2017
282017
A fast process variation and pattern fidelity aware mask optimization algorithm
A Awad, A Takahashi, S Tanaka, C Kodama
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 238-245, 2014
282014
Method for manufacturing semiconductor device
H Mashita, T Kotani, H Mukai, F Nakajima, C Kodama
US Patent 7,713,833, 2010
282010
Linear programming-based cell placement with symmetry constraints for analog IC layout
S Koda, C Kodama, K Fujiyoshi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
262007
Semiconductor device and method of manufacturing the same
F Nakajima, T Kotani, H Mashita, T Taguchi, R Aburada, C Kodama
US Patent App. 13/234,052, 2012
202012
Sub-resolution assist feature arranging method and computer program product and manufacturing method of semiconductor device
C Kodama, T Kotani, S Nojima, S Mimotogi
US Patent 8,809,072, 2014
192014
Mask-layout creating method, apparatus therefor, and computer program product
K Kodera, C Kodama
US Patent 8,336,006, 2012
192012
Nonvolatile semiconductor storage device and method of manufacturing the same
R Aburada, T Kotani, T Taguchi, C Kodama
US Patent App. 12/858,986, 2011
182011
Semiconductor device
C Kodama, M Ito
US Patent 7,777,348, 2010
182010
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods
C Kodama, H Ichikawa, K Nakayama, F Nakajima, S Nojima, T Kotani, ...
IEEE Transactions on Computer Aided Design of Integrated Circuits and …, 2015
172015
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography
Y Kohira, T Matsui, Y Yokoyama, C Kodama, A Takahashi, S Nojima, ...
The 20th Asia and South Pacific Design Automation Conference, 665-670, 2015
142015
Method of fabricating semiconductor device and semiconductor device
R Aburada, H Mashita, T Kotani, C Kodama
US Patent 8,183,148, 2012
142012
A fast process-variation-aware mask optimization algorithm with a novel intensity modeling
A Awad, A Takahashi, S Tanaka, C Kodama
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3), 998 …, 2016
132016
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Articles 1–20