Memory device and memory system including the same for controlling collision between access operation and refresh operation WJ Choi, Y Hui-Kap US Patent App. 15/340,345, 2017 | 51 | 2017 |
A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 41 | 2008 |
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 23 | 2018 |
A 1.6 V 3.3 Gb/s GDDR3 DRAM with dual-mode phase-and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS HW Lee, WJ Yun, YK Choi, HH Choi, JJ Lee, KH Kim, SD Kang, JY Yang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 8 | 2009 |
Sense amplifier screen circuit and screen method thereof WJ Choi US Patent 7,656,728, 2010 | 7 | 2010 |
A low power digital DLL with wide locking range for 3Gbps 512Mb GDDR3 SDRAM WJ Yun, HW Lee, YJ Kim, WJ Choi, SH Shin, HH Choi, HO Lee, SD Kang, ... 2006 IEEE Asian Solid-State Circuits Conference, 323-326, 2006 | 5 | 2006 |
Word line driving circuit and method of testing a word line using the word line driving circuit JW Lee, HW Moon, WJ Choi US Patent 7,715,259, 2010 | 3 | 2010 |
Address counting circuit and semiconductor memory apparatus using the same SH Shin, WJ Choi US Patent 7,911,875, 2011 | 1 | 2011 |
Semiconductor memory apparatus HW Moon, JW Lee, WJ Choi US Patent 7,826,300, 2010 | | 2010 |
Fuse information control device, semiconductor integrated circuit using the same, and control method thereof WJ Choi, JW Lee, HW Moon US Patent App. 12/347,228, 2009 | | 2009 |