| An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture H Makino, Y Nakase, H Suzuki, H Morinaka, H Shinohara, K Mashiko IEEE Journal of Solid-State Circuits 31 (6), 773-783, 1996 | 230 | 1996 |
| Leading-zero anticipatory logic for high-speed floating point addition H Suzuki, H Morinaka, H Makino, Y Nakase, K Mashiko, T Sumi IEEE Journal of Solid-State Circuits 31 (8), 1157-1164, 1996 | 163 | 1996 |
| Fast tag comparator using diode partitioned domino for 64-bit microprocessors H Suzuki, CH Kim, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 54 (2), 322-328, 2007 | 66 | 2007 |
| A 64 bit carry look-ahead CMOS adder using Modified Carry Select H Morinaka, H Makino, Y Nakase, H Suzuki, K Mashiko Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 585-588, 1995 | 37 | 1995 |
| A 64-bit carry look ahead adder using pass transistor BiCMOS gates K Ueda, H Suzuki, K Suda, H Shinohara, K Mashiko IEEE journal of Solid-State circuits 31 (6), 810-818, 1996 | 33 | 1996 |
| Low power adder with adaptive supply voltage H Suzuki, W Jeong, K Roy Proceedings 21st International Conference on Computer Design, 103-106, 2003 | 32 | 2003 |
| A 286 MHz 64-b floating point multiplier with enhanced CG operation H Makino, H Suzuki, H Morinaka, Y Nakase, K Mashiko, T Sumi IEICE transactions on electronics 79 (7), 915-924, 1996 | 23 | 1996 |
| On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect M Fujii, H Suzuki, H Notani, H Makino, H Shinohara ESSCIRC 2008-34th European Solid-State Circuits Conference, 258-261, 2008 | 9 | 2008 |
| Novel VLIW code compaction method for a 3D geometry processor H Suzuki, H Kawai, H Makino, Y Matsuda IEICE transactions on fundamentals of electronics, communications and …, 2001 | 9 | 2001 |
| A 2.6-ns 64-b fast and small CMOS adder H Morinaka, H Makino, Y Nakase, H Suzuki, K Mashiko, T Sumi IEICE transactions on electronics 79 (4), 530-537, 1996 | 7 | 1996 |
| A 64-bit adder by pass transistor BiCMOS circuit K Ueda, H Suzuki, K Suda, Y Tsujihashi, H Shinohara Proceedings of IEEE Custom Integrated Circuits Conference-CICC'93, 12.2. 1 …, 1993 | 5 | 1993 |
| 1.047 GHz, 1.2 V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit H Suzuki, H Takata, H Shinohara, E Teraoka, M Matsuo, T Yoshida, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 152-153, 2006 | 4 | 2006 |
| A programmable geometry processor with enhanced four-parallel SIMD type processing core for PC-based 3D graphics H Kawai, Y Inoue, J Kobara, R Streitenberger, H Suzuki, H Negishi, ... IEICE transactions on electronics 85 (5), 1200-1210, 2002 | 4 | 2002 |
| A design of high-speed 4-2 compressor for fast multiplier H Makino, H Suzuki, H Morinaka, Y Nakase, H Shinohara, K Mashiko, ... IEICE transactions on electronics 79 (4), 538-548, 1996 | 4 | 1996 |
| A BiCMOS wired-OR logic Y Nakase, H Suzuki, H Makino, H Shinohara, K Mashiko IEEE journal of solid-state circuits 30 (6), 622-628, 1995 | 4 | 1995 |
| Signal integrity design and analysis for a 400 MHz RISC microcontroller A YAMADA, Y NUNOMURA, H SUZUKI, H SATO, N ITOH, T KAGEMOTO, ... IEICE transactions on electronics 86 (4), 635-642, 2003 | 3 | 2003 |
| A floating-point divider using redundant binary circuits and an asynchronous clock scheme H SUZUKI, H MAKINO, K MASHIKO IEICE transactions on electronics 82 (1), 105-110, 1999 | 2 | 1999 |
| Adaptive supply voltage for low-power ripple-carry and carry-select adders H Suzuki, W Jeong, K Roy IEICE transactions on electronics 90 (4), 865-876, 2007 | 1 | 2007 |
| Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology H Suzuki, M Kurimoto, T Yamanaka, H Takata, H Makino, H Shinohara Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | | 2008 |
