| Evaluation of fine grain 3-D integrated arithmetic units R Egawa, J Taday, H Kobayashi, G Gotoy 2009 IEEE International Conference on 3D System Integration, 1-8, 2009 | 21 | 2009 |
| A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers J Tada, R Egawa, K Kawai, H Kobayashi, G Goto 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2012 | 12 | 2012 |
| Complex Multiplier suited for EPGA structure K Satoh, J Tada, K Yamaguchi, Y Tamura ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2008 | 11 | 2008 |
| Vertically integrated processor and memory module design for vector supercomputers R Egawa, M Sato, J Tada, H Kobayashi 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013 | 10 | 2013 |
| P2b-6 parallel image reconstruction operation by dedicated hardware for three-dimensional ultrasound imaging K Satoh, J Tada, H Yanagida, Y Tamura 2007 IEEE Ultrasonics Symposium Proceedings, 1522-1525, 2007 | 9 | 2007 |
| An adaptive demotion policy for high-associativity caches J Tada, M Sato, R Egawa Proceedings of the 8th International Symposium on Highly Efficient …, 2017 | 8 | 2017 |
| Three-dimensional ultrasonic imaging operation using FPGA K Satoh, J Tada, Y Tamura IEICE Electronics Express 6 (2), 84-89, 2009 | 4 | 2009 |
| A cache replacement policy with considering global fluctuations of priority values J Tada International Journal of Networking and Computing 9 (2), 161-170, 2019 | 3 | 2019 |
| An impact of circuit scale on the performance of 3-D stacked arithmetic units J Tada, R Egawa, H Kobayashi 2014 International 3D Systems Integration Conference (3DIC), 1-5, 2014 | 3 | 2014 |
| Design of a 3-D stacked floating-point adder J Tada, R Egawa, H Kobayashi 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2013 | 3 | 2013 |
| Edge-connected, crossed-electrode array comprising non-linear transducers I Fujishima, Y Tamura, H Yanagida, J Tada, T Takahashi 2009 IEEE International Ultrasonics Symposium, 2221-2224, 2009 | 3 | 2009 |
| An Implementation of a Grid Square Codes Generator on a RISC-V Processor J Tada, K Sato 2020 Eighth International Symposium on Computing and Networking Workshops …, 2020 | 2 | 2020 |
| Performance evaluation of 3-D stacked 32-bit parallel multipliers J Tada ACM SIGARCH Computer Architecture News 41 (5), 89-94, 2014 | 2 | 2014 |
| Gain based delay balancing in the deep submicron era R Egawa, T Jubee, H Kobayashi, G Gensuke ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2008 | 2 | 2008 |
| A Sophisticated Multiplier in Advanced CMOS Technologies R Egawa, J Tada, G Goto, T Nakamura ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2006 | 2 | 2006 |
| An Implementation of a Grid Square Codes Generator on a RISC-V Processor J Tada, K Sato International Journal of Networking and Computing 12 (1), 204-217, 2022 | 1 | 2022 |
| A Cache Replacement Policy with Considering Fluctuation Patterns of Total Priority Value J Tada, R Higashi 2019 Seventh International Symposium on Computing and Networking Workshops …, 2019 | 1 | 2019 |
| A cache replacement policy with considering global fluctuations of priority values J Tada 2018 Sixth International Symposium on Computing and Networking Workshops …, 2018 | 1 | 2018 |
| Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units J Tada, M Hosokawa, R Egawa, H Kobayashi ACM SIGARCH Computer Architecture News 44 (4), 62-67, 2017 | 1 | 2017 |
| A power-aware LLC control mechanism for the 3D-stacked memory system R Egawa, W Uno, M Sato, H Kobayashi, J Tada 2016 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2016 | 1 | 2016 |
