Takeshi Fujino
Takeshi Fujino
Verified email at se.ritsumei.ac.jp - Homepage
Title
Cited by
Cited by
Year
Dynamic semiconductor memory device
T Fujino, K Arimoto
US Patent 6,151,244, 2000
3142000
Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for …
K Arimoto, H Shimano, T Fujino, T Hashizume
US Patent 6,449,204, 2002
982002
Semiconductor memory device suitable for merging with logic
N Watanabe, A Yamazaki, K Arimoto, T Fujino, I Hayashi, H Noda
US Patent 6,418,067, 2002
512002
Reversing stealthy dopant-level circuits
T Sugawara, D Suzuki, R Fujii, S Tawa, R Hori, M Shiozaki, T Fujino
International Workshop on Cryptographic Hardware and Embedded Systems, 112-126, 2014
482014
Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement
T Tanizaki, M Kinoshita, T Fujino, T Tsuruda, F Morishita, T Amano, ...
US Patent 6,064,621, 2000
472000
Semiconductor memory device capable of increasing chip yields while maintaining rapid operation
M Kobayashi, T Tanizaki, K Arimoto, T Amano, T Fujino, T Tsuruda, ...
US Patent 5,914,907, 1999
451999
On measurable side-channel leaks inside ASIC design primitives
T Sugawara, D Suzuki, M Saeki, M Shiozaki, T Fujino
International Conference on Cryptographic Hardware and Embedded Systems, 159-178, 2013
432013
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with delay-time measurement
K Fruhashi, M Shiozaki, A Fukushima, T Murayama, T Fujino
2011 IEEE international symposium of circuits and systems (ISCAS), 2325-2328, 2011
382011
Refresh-free dynamic semiconductor memory device
K Arimoto, H Shimano, T Fujino, T Hashizume
US Patent 6,925,022, 2005
382005
Tamper-resistant memory integrated circuit and encryption circuit using same
T Fujino
US Patent 8,861,720, 2014
342014
0.15/spl mu/m CMOS process for high performance and high reliability
S Shimizu, T Kuroi, M Kobayashi, T Yamaguchi, T Fujino, H Maeda, ...
Proceedings of 1994 IEEE International Electron Devices Meeting, 67-70, 1994
321994
Sputtered w-ti film for x-ray mask absorber
H Yabe, K Marumoto, S Aya, N Yoshioka, T Fujino, Y Watakabe, Y Matsui
Japanese journal of applied physics 31 (12S), 4210, 1992
321992
Refresh-free dynamic semiconductor memory device
K Arimoto, H Shimano, T Fujino, T Hashizume
US Patent 7,139,208, 2006
312006
Hierarchical image-scrambling method with scramble-level controllability for privacy protection
T Honda, Y Murakami, Y Yanagihara, T Kumaki, T Fujino
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
292013
Multichannel optical diagnostic system for field-reversed configuration plasmas
T Takahashi, H Gota, T Fujino, M Okada, T Asai, K Fujimoto, Y Ohkuma, ...
Review of scientific instruments 75 (12), 5205-5212, 2004
272004
Diffusion Programmable Device: The device to prevent reverse engineering.
M Shiozaki, R Hori, T Fujino
IACR Cryptol. ePrint Arch. 2014, 109, 2014
262014
Semiconductor memory device having row-related circuit operating at high speed
T Fujino, K Inoue, A Yamazaki, K Arimoto
US Patent 6,507,532, 2003
262003
Semiconductor memory device storing redundant replacement information with small occupation area
M Haraguchi, T Fujino
US Patent 7,254,069, 2007
232007
Character-build standard-cell layout technique for high-throughput character-projection EB lithography
T Fujino, Y Kajiya, M Yoshikawa
Photomask and Next-Generation Lithography Mask Technology XII 5853, 160-167, 2005
232005
Low power consumption semiconductor memory
T Fujino
US Patent App. 10/028,801, 2002
232002
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