PUF modeling attacks on simulated and silicon data U Rührmair, J Sölter, F Sehnke, X Xu, A Mahmoud, V Stoyanova, G Dror, ... IEEE transactions on information forensics and security 8 (11), 1876-1891, 2013 | 646 | 2013 |
Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks X Xu, B Shakya, MM Tehranipoor, D Forte (CHES) International conference on cryptographic hardware and embedded …, 2017 | 210 | 2017 |
Efficient power and timing side channels for physical unclonable functions U Rührmair, X Xu, J Sölter, A Mahmoud, M Majzoobi, F Koushanfar, ... (CHES) International Workshop on Cryptographic Hardware and Embedded Systems …, 2014 | 171 | 2014 |
Hybrid side-channel/machine-learning attacks on PUFs: A new threat? X Xu, W Burleson 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 96 | 2014 |
CAS-Lock: A security-corruptibility trade-off resilient logic locking scheme B Shakya, X Xu, M Tehranipoor, D Forte (CHES) IACR Transactions on Cryptographic Hardware and Embedded Systems, 175-202, 2020 | 93 | 2020 |
Electronics supply chain integrity enabled by blockchain X Xu, F Rahman, B Shakya, A Vassilev, D Forte, M Tehranipoor ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (3 …, 2019 | 86 | 2019 |
Power-based side-channel instruction-level disassembler J Park, X Xu, Y Jin, D Forte, M Tehranipoor Proceedings of the 55th Annual Design Automation Conference (DAC), 1-6, 2018 | 80 | 2018 |
Security evaluation and enhancement of bistable ring PUFs X Xu, U Rührmair, DE Holcomb, W Burleson 11th International Workshop, RFIDsec 2015, New York, NY, USA, June 23-24 …, 2015 | 65 | 2015 |
Development and evaluation of hardware obfuscation benchmarks S Amir, B Shakya, X Xu, Y Jin, S Bhunia, M Tehranipoor, D Forte Journal of Hardware and Systems Security 2, 142-161, 2018 | 64 | 2018 |
Virtual proofs of reality and their physical implementation U Rührmair, JL Martinez-Hurtado, X Xu, C Kraeh, C Hilgers, D Kononchuk, ... 2015 IEEE symposium on security and privacy (SP), 70-85, 2015 | 62 | 2015 |
Reliable physical unclonable functions using data retention voltage of SRAM cells X Xu, A Rahmati, DE Holcomb, K Fu, W Burleson IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 52 | 2015 |
Using statistical models to improve the reliability of delay-based PUFs X Xu, W Burleson, DE Holcomb 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 547-552, 2016 | 50 | 2016 |
{Deep-Dup}: An adversarial weight duplication attack framework to crush deep neural network in {Multi-Tenant}{FPGA} AS Rakin, Y Luo, X Xu, D Fan 30th USENIX Security Symposium (USENIX Security 21), 1919-1936, 2021 | 49 | 2021 |
Power and timing side channels for PUFs and their efficient exploitation U Rührmair, X Xu, J Sölter, A Mahmoud, F Koushanfar, W Burleson Cryptology ePrint Archive, 2013 | 39 | 2013 |
HILL: A hardware isolation framework against information leakage on multi-tenant FPGA long-wires Y Luo, X Xu 2019 International Conference on Field-Programmable Technology (ICFPT), 331-334, 2019 | 30 | 2019 |
Security beyond CMOS: fundamentals, applications, and roadmap F Rahman, B Shakya, X Xu, D Forte, M Tehranipoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 30 | 2017 |
Deepstrike: Remotely-guided fault injection attacks on dnn accelerator in cloud-fpga Y Luo, C Gongye, Y Fei, X Xu 2021 58th ACM/IEEE Design Automation Conference (DAC), 295-300, 2021 | 26 | 2021 |
SCARe: an SRAM-based countermeasure against IC recycling Z Guo, X Xu, MT Rahman, MM Tehranipoor, D Forte IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (4), 744-755, 2017 | 24 | 2017 |
A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA Y Luo, X Xu 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2020 | 23 | 2020 |
A privacy-preserving-oriented dnn pruning and mobile acceleration framework Y Gong, Z Zhan, Z Li, W Niu, X Ma, W Wang, B Ren, C Ding, X Lin, X Xu, ... Proceedings of the 2020 on Great Lakes Symposium on VLSI, 119-124, 2020 | 23 | 2020 |