Atsushi Matsuo
Atsushi Matsuo
IBM Research
確認したメール アドレス: jp.ibm.com
タイトル
引用先
引用先
Changing the gate order for optimal LNN conversion
A Matsuo, S Yamashita
International workshop on reversible computation, 89-101, 2011
352011
Optimization of quantum circuit mapping using gate transformation and commutation
T Itoko, R Raymond, T Imamichi, A Matsuo
Integration 70, 43-50, 2020
302020
Reducing the overhead of mapping quantum circuits to IBM Q system
A Matsuo, W Hattori, S Yamashita
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
162019
Quantum circuit compilers using gate commutation rules
T Itoko, R Raymond, T Imamichi, A Matsuo, AW Cross
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
162019
An efficient method for quantum circuit placement problem on a 2-D grid
A Matsuo, S Yamashita
International conference on reversible computation, 162-168, 2019
62019
IEICE Technical Report
M Ohno, Y Kamiya, S Matsubara, A Kato, Y Nankaku, A Lee, K Tokuda, ...
Pattern Recognition 106 (469), 2005
32005
Problem-specific parameterized quantum circuits of the VQE algorithm for optimization problems
A Matsuo, Y Suzuki, S Yamashita
arXiv preprint arXiv:2006.05643, 2020
22020
Automatic generation of ising hamiltonians for solving optimization problems in quantum computing
A Matsuo, T Imamichi, M Pistoia
US Patent App. 16/356,608, 2020
12020
System and method for handling inequality constraints in mixed binary optimization on quantum computers
S Woerner, DJ Egger, JR Glick, T Imamichi, A Matsuo
US Patent App. 16/739,591, 2021
2021
Variational Quantum Eigensolver and Its Applications
A Matsuo
International Conference on Reversible Computation, 22-41, 2021
2021
Mapping logical qubits on a quantum circuit
T Itoko, A Matsuo
US Patent 11,010,518, 2021
2021
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures
A Matsuo, W Hattori, S Yamashita
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 786-791, 2021
2021
Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems
SY Atsushi Matsuo, Yudai Suzuki
arXiv preprint arXiv:2006.05643, 2020
2020
Mapping logical qubits on a quantum circuit
T Itoko, A Matsuo
US Patent 10,657,304, 2020
2020
Fault-Tolerant Design with Less Overhead than DMR
A Matsuo, S Yamashita
IEICE Technical Report; IEICE Tech. Rep. 113 (320), 33-37, 2013
2013
Partially-Programmable Circuits with CAMs
A Matsuo, S Yamashita, H Yoshida
IEICE Technical Report; IEICE Tech. Rep. 112 (320), 31-36, 2012
2012
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