Tetsu TANAKA
Tetsu TANAKA
Tohoku University (2005-), Fujitsu laboratories (1990-2005)
確認したメール アドレス: lbc.mech.tohoku.ac.jp - ホームページ
タイトル引用先
Scaling theory for double-gate SOI MOSFET's
K Suzuki, T Tanaka, Y Tosaka, H Horie, Y Arimoto
IEEE Transactions on Electron Devices 40 (12), 2326-2329, 1993
5751993
High-density through silicon vias for 3-D LSIs
M Koyanagi, T Fukushima, T Tanaka
Proceedings of the IEEE 97 (1), 49-59, 2009
2962009
Three-dimensional integration technology based on wafer bonding with vertical buried interconnections
M Koyanagi, T Nakamura, Y Yamada, H Kikuchi, T Fukushima, T Tanaka, ...
IEEE Transactions on Electron Devices 53 (11), 2799-2808, 2006
2372006
A comparative study of advanced MOSFET concepts
CH Wann, K Noda, T Tanaka, M Yoshida, C Hu
IEEE Transactions on Electron Devices 43 (10), 1742-1753, 1996
2361996
Memory cell array, method of producing the same, and semiconductor memory device using the same
E Yoshida, T Tanaka, T Miyashita
US Patent 7,671,417, 2010
1422010
Three-dimensional integration technology and integrated systems
M Koyanagi, T Fukushima, T Tanaka
2009 Asia and South Pacific Design Automation Conference, 409-415, 2009
1412009
Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM
T Tanaka, E Yoshida, T Miyashita
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
1382004
A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory
E Yoshida, T Tanaka
IEEE Transactions on Electron Devices 53 (4), 692-697, 2006
1372006
Ultrafast operation of V/sub th/-adjusted p/sup+/-n/sup+/double-gate SOI MOSFET's
T Tanaka, K Suzuki, H Horie, T Sugii
IEEE Electron Device Letters 15 (10), 386-388, 1994
1071994
New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique
T Fukushima, H Kikuchi, Y Yamada, T Konno, J Liang, K Sasaki, ...
2007 IEEE International Electron Devices Meeting, 985-988, 2007
1002007
Three-dimensional hybrid integration technology of CMOS, MEMS, and photonics circuits for optoelectronic heterogeneous integrated systems
KW Lee, A Noriki, K Kiyoyama, T Fukushima, T Tanaka, M Koyanagi
IEEE Transactions on Electron Devices 58 (3), 748-757, 2010
922010
Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits
T Fukushima, E Iwata, T Konno, JC Bea, KW Lee, T Tanaka, M Koyanagi
Applied Physics Letters 96 (15), 154105, 2010
862010
Analysis of p/sup+/poly Si double-gate thin-film SOI MOSFETs
T Tanaka, H Horie, S Ando, S Hijiya
International Electron Devices Meeting 1991 [Technical Digest], 683-686, 1991
811991
Tungsten through-silicon via technology for three-dimensional LSIs
H Kikuchi, Y Yamada, AM Ali, J Liang, T Fukushima, T Tanaka, ...
Japanese Journal of Applied Physics 47 (4S), 2801, 2008
762008
Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias
M Murugesan, H Kino, H Nohira, JC Bea, A Horibe, F Yamada, ...
2010 International Electron Devices Meeting, 2.3. 1-2.3. 4, 2010
712010
Analytical surface potential expression for thin-film double-gate SOI MOSFETs
K Suzuki, T Tanaka, Y Tosaka, H Horie, Y Arimoto, T Itoh
Solid-state electronics 37 (2), 327-332, 1994
711994
Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method
T Fukushima, E Iwata, Y Ohara, A Noriki, K Inamura, KW Lee, J Bea, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
542009
New heterogeneous multi-chip module integration technology using self-assembly method
T Fukushima, T Konno, K Kiyoyama, M Murugesan, K Sato, WC Jeong, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
502008
A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process
KI Goto, J Matsuo, Y Tada, T Tanaka, Y Momiyama, T Sugii, I Yamada
International Electron Devices Meeting. IEDM Technical Digest, 471-474, 1997
481997
Multichip self-assembly technology for advanced die-to-wafer 3-D integration to precisely align known good dies in batch processing
T Fukushima, E Iwata, Y Ohara, M Murugesan, J Bea, K Lee, T Tanaka, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 …, 2011
472011
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論文 1–20