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Kodai Ueyoshi
Kodai Ueyoshi
Preferred Networks, Inc.
Verified email at ist.hokudai.ac.jp
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Cited by
Year
BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ...
IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017
1672017
QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018
1002018
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ...
2017 Symposium on VLSI Circuits, C24-C25, 2017
932017
QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ...
IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018
582018
DIANA: An end-to-end energy-efficient digital and analog hybrid neural network SoC
K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
422022
Diana: An end-to-end hybrid digital and analog neural network soc for the edge
P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ...
IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022
242022
A 96-MB 3D-stacked SRAM using inductive coupling with 0.4-V transmitter, termination scheme and 12: 1 SerDes in 40-nm CMOS
K Shiba, T Omori, K Ueyoshi, S Takamaeda-Yamazaki, M Motomura, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 692-703, 2020
222020
Error tolerance analysis of deep learning hardware using a restricted boltzmann machine toward low-power memory implementation
T Marukame, K Ueyoshi, T Asai, M Motomura, A Schmid, M Suzuki, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (4), 462-466, 2016
222016
FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines
K Ueyoshi, T Marukame, T Asai, M Motomura, A Schmid
Circuits and Systems 7 (09), 2132, 2016
172016
Dither nn: An accurate neural network with dithering for low bit-precision hardware
K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ...
2018 International Conference on Field-Programmable Technology (FPT), 6-13, 2018
112018
In-memory area-efficient signal streaming processor design for binary neural networks
H Yonekawa, S Sato, H Nakahara, K Ando, K Ueyoshi, K Hirose, K Orimo, ...
2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017
92017
Quantization error-based regularization for hardware-aware neural network training
K Hirose, R Uematsu, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ...
Nonlinear Theory and Its Applications, IEICE 9 (4), 453-465, 2018
72018
Fpga architecture for feed-forward sequential memory network targeting long-term time-series forecasting
K Orimo, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
72016
Quantization error-based regularization in neural networks
K Hirose, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ...
Artificial Intelligence XXXIV: 37th SGAI International Conference on …, 2017
62017
Scalable and highly parallel architecture for restricted boltzmann machines
K Ueyoshi, T Asai, M Motomura
Proc. RISP International Workshop on Nonlinear Circuits, Communications and …, 2015
62015
Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing
K Ueyoshi, T Marukame, T Asai, M Motomura, A Schmid
Nonlinear Theory and Its Applications, IEICE 7 (3), 395-406, 2016
52016
Exploring optimized accelerator design for binarized convolutional neural networks
K Ueyoshi, K Ando, K Orimo, M Ikebe, T Asai, M Motomura
2017 International Joint Conference on Neural Networks (IJCNN), 2510-2516, 2017
42017
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in deep belief network
K Ueyoshi, T Marukame, T Asai, M Motomura, A Schmid
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 357-360, 2016
42016
A 3D-stacked SRAM using inductive coupling with low-voltage transmitter and 12: 1 SerDes
K Shiba, T Omori, K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, ...
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
32020
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ...
IEICE TRANSACTIONS on Information and Systems 102 (12), 2341-2353, 2019
32019
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