| BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 187 | 2017 |
| QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018 | 104 | 2018 |
| BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 97 | 2017 |
| DIANA: An end-to-end energy-efficient digital and ANAlog hybrid neural network SoC K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 69 | 2022 |
| QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ... IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018 | 59 | 2018 |
| Diana: An end-to-end hybrid digital and analog neural network soc for the edge P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ... IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022 | 48 | 2022 |
| Error tolerance analysis of deep learning hardware using a restricted boltzmann machine toward low-power memory implementation T Marukame, K Ueyoshi, T Asai, M Motomura, A Schmid, M Suzuki, ... IEEE Transactions on Circuits and Systems II: Express Briefs 64 (4), 462-466, 2016 | 23 | 2016 |
| A 96-MB 3D-stacked SRAM using inductive coupling with 0.4-V transmitter, termination scheme and 12: 1 SerDes in 40-nm CMOS K Shiba, T Omori, K Ueyoshi, S Takamaeda-Yamazaki, M Motomura, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 692-703, 2020 | 22 | 2020 |
| FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines K Ueyoshi, T Marukame, T Asai, M Motomura, A Schmid Circuits and Systems 7 (9), 2132-2141, 2016 | 17 | 2016 |
| Dither nn: An accurate neural network with dithering for low bit-precision hardware K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ... 2018 International Conference on Field-Programmable Technology (FPT), 6-13, 2018 | 13 | 2018 |
| In-memory area-efficient signal streaming processor design for binary neural networks H Yonekawa, S Sato, H Nakahara, K Ando, K Ueyoshi, K Hirose, K Orimo, ... 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 10 | 2017 |
| Quantization error-based regularization in neural networks K Hirose, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ... Artificial Intelligence XXXIV: 37th SGAI International Conference on …, 2017 | 9 | 2017 |
| Quantization error-based regularization for hardware-aware neural network training K Hirose, R Uematsu, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ... Nonlinear Theory and Its Applications, IEICE 9 (4), 453-465, 2018 | 7 | 2018 |
| Fpga architecture for feed-forward sequential memory network targeting long-term time-series forecasting K Orimo, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura 2016 International Conference on ReConFigurable Computing and FPGAs …, 2016 | 7 | 2016 |
| Scalable and highly parallel architecture for restricted boltzmann machines K Ueyoshi, T Asai, M Motomura Proc. RISP International Workshop on Nonlinear Circuits, Communications and …, 2015 | 6 | 2015 |
| A 3D-stacked SRAM using inductive coupling with low-voltage transmitter and 12: 1 SerDes K Shiba, T Omori, K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, ... 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 5 | 2020 |
| Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing K Ueyoshi, T Marukame, T Asai, M Motomura, A Schmid Nonlinear Theory and Its Applications, IEICE 7 (3), 395-406, 2016 | 5 | 2016 |
| Neural electronic circuit S Takamaeda, K Ueyoshi, M Motomura US Patent App. 16/967,551, 2021 | 4 | 2021 |
| Area and energy optimization for bit-serial log-quantized DNN accelerator with shared accumulators T Kudo, K Ueyoshi, K Ando, K Hirose, R Uematsu, Y Oba, M Ikebe, T Asai, ... 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018 | 4 | 2018 |
| Exploring optimized accelerator design for binarized convolutional neural networks K Ueyoshi, K Ando, K Orimo, M Ikebe, T Asai, M Motomura 2017 International Joint Conference on Neural Networks (IJCNN), 2510-2516, 2017 | 4 | 2017 |
