| Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration Y Ichinomiya, S Tanoue, M Amagasaki, M Iida, M Kuga, T Sueyoshi 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010 | 83 | 2010 |
| An easily testable routing architecture and prototype chip K Inoue, M Koga, M Amagasaki, M Iida, Y Ichida, M Saji, J Iida, ... IEICE TRANSACTIONS on Information and Systems 95 (2), 303-313, 2012 | 24 | 2012 |
| COGRE: A configuration memory reduced reconfigurable logic cell architecture for area minimization Y Okamoto, Y Ichinomiya, M Amagasaki, M Iida, T Sueyoshi 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 24 | 2010 |
| Configurable and reconfigurable computing for digital signal processing T Sueyoshi, M Iida IEICE transactions on fundamentals of electronics, communications and …, 2002 | 22 | 2002 |
| A novel soft error detection and correction circuit for embedded reconfigurable systems Q Zhao, Y Ichinomiya, M Amagasaki, M Iida, T Sueyoshi IEEE Embedded Systems Letters 3 (3), 89-92, 2011 | 21 | 2011 |
| A bitstream relocation technique to improve flexibility of partial reconfiguration Y Ichinomiya, M Amagasaki, M Iida, M Kuga, T Sueyoshi Algorithms and Architectures for Parallel Processing: 12th International …, 2012 | 17 | 2012 |
| An embedded reconfigurable IP core with variable grain logic cell architecture M Amagasaki, R Yamaguchi, M Koga, M Iida, T Sueyoshi International Journal of Reconfigurable Computing 2008, 2008 | 16 | 2008 |
| Designing flexible reconfigurable regions to relocate partial bitstreams Y Ichinomiya, S Usagawa, M Amagasaki, M Iida, M Kuga, T Sueyoshi 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012 | 14 | 2012 |
| Enabling FPGA-as-a-service in the cloud with hCODE platform Q Zhao, M Amagasaki, M Iida, M Kuga, T Sueyoshi IEICE TRANSACTIONS on Information and Systems 101 (2), 335-343, 2018 | 13 | 2018 |
| FPGA design framework combined with commercial VLSI CAD Q Zhao, K Inoue, M Amagasaki, M Iida, M Kuga, T Sueyoshi IEICE TRANSACTIONS on Information and Systems 96 (8), 1602-1612, 2013 | 13 | 2013 |
| A heuristic method of generating diameter 3 graphs for order/degree problem T Kitasuka, M Iida 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-6, 2016 | 12 | 2016 |
| Reconfigurable computing T Sueyoshi, M Iida Proc. 5th Jpn. FPGA/PLD Design Conf. & Exhibit, 139-148, 1997 | 12 | 1997 |
| A study of heterogeneous computing design method based on virtualization technology Q Zhao, M Amagasaki, M Iida, M Kuga, T Sueyoshi ACM SIGARCH Computer Architecture News 44 (4), 86-91, 2017 | 11 | 2017 |
| Direct Metallization Technology, Part I H Nakahara Print Circ Fab 15 (10), 16-19, 1992 | 11* | 1992 |
| An easily testable routing architecture and efficient test technique K Inoue, H Yosho, M Amagasaki, M Iida, T Sueyoshi 2011 21st International Conference on Field Programmable Logic and …, 2011 | 10 | 2011 |
| Improving the Soft-error Tolerability of a Softcore Processor on an FPGA using Triple Modular Redundancy and Partial Reconfiguration Y Ichinomiya JNIT: Jounal of Next Generation Information Technology 2 (3), 35-48, 2011 | 10 | 2011 |
| Defect-robust FPGA architectures for intellectual property cores in system LSI M Amagasaki, K Inoue, Q Zhao, M Iida, M Kuga, T Sueyoshi 2013 23rd International Conference on Field programmable Logic and …, 2013 | 9 | 2013 |
| What is an FPGA? M Iida Principles and Structures of FPGAs, 23-45, 2018 | 8 | 2018 |
| Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block T Sueyoshi, M Iida, M Amagasaki, K Taketa, T Heishi, N Suzuki US Patent 8,587,336, 2013 | 8 | 2013 |
| An automatic FPGA design and implementation framework Q Zhao, M Amagasaki, M Iida, M Kuga, T Sueyoshi 2013 23rd International Conference on Field programmable Logic and …, 2013 | 8 | 2013 |
