フォロー
Hiroaki Iwashita
Hiroaki Iwashita
確認したメール アドレス: fujitsu.com
タイトル
引用先
引用先
CTL model checking based on forward state traversal
H Iwashita, T Nakata, F Hirose
Proceedings of International Conference on Computer Aided Design, 82-87, 1996
991996
Automatic test program generation for pipelined processors
H Iwashita, S Kowatari, T Nakata, F Hirose
ICCAD 94, 580-583, 1994
951994
Frontier-based search for enumerating all constrained subgraphs with compressed representation
J Kawahara, T Inoue, H Iwashita, S Minato
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017
932017
Graphillion: software library for very large sets of labeled graphs
T Inoue, H Iwashita, J Kawahara, S Minato
International Journal on Software Tools for Technology Transfer 18, 57-66, 2016
712016
Forward model checking techniques oriented to buggy designs
Iwashita, Nakata
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
561997
Finding all solutions and instances of numberlink and slitherlink by ZDDs
R Yoshinaka, T Saitoh, J Kawahara, K Tsuruma, H Iwashita, S Minato
Algorithms 5 (20), 176-213, 2012
532012
Efficient top-down ZDD construction techniques using recursive specifications
H Iwashita, S Minato
Hokkaido University Division of Computer Science TCS Technical Report TCS-TR …, 2013
492013
Efficient computation of the number of paths in a grid graph with minimal perfect hash functions
H Iwashita, Y Nakazawa, J Kawahara, T Uno, S Minato
TCS Technical Report. No. TCS-TR-A-13-64. Hokkaido University Division of …, 2013
312013
Verification support of circuit blocks having independent clock domains
H Iwashita
US Patent 8,533,541, 2013
292013
Verification support of circuit blocks having independent clock domains
H Iwashita
US Patent 8,533,541, 2013
292013
Method and apparatus for supporting verification, and computer product
H Iwashita
US Patent 7,464,015, 2008
292008
Clock domain crossing verification support
H Iwashita
US Patent 8,407,636, 2013
282013
Clock domain crossing verification support
H Iwashita
US Patent 8,407,636, 2013
282013
Apparatus, method, and storage medium for verifying logical device
H Iwashita
US Patent 6,654,715, 2003
212003
Logical device verification method and apparatus
H Iwashita, T Nakata
US Patent 6,141,633, 2000
212000
Simplifying urban network security games with cut-based graph contraction
H Iwashita, K Ohori, H Anai, A Iwasaki
Proceedings of the 2016 International Conference on Autonomous Agents …, 2016
172016
ZDD-based computation of the number of paths in a graph
H Iwashita, J Kawahara, S Minato
Hokkaido University Division of Computer Science TCS Technical Report TCSTR …, 2012
152012
Logic verification device, logic verification method, and computer product
H Iwashita
US Patent 7,194,713, 2007
142007
System for automatic generating instruction string to verify pipeline operations of a processor by inputting specification information having time for the processor to access …
H Iwashita
US Patent 5,673,425, 1997
141997
Integrated design and test assistance for pipeline controllers
H Iwashita, T Nakata, F Hirose
IEICE TRANSACTIONS on Information and Systems 76 (7), 747-754, 1993
131993
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