Follow
Teerachot Siriburanon
Teerachot Siriburanon
Verified email at ucd.ie - Homepage
Title
Cited by
Cited by
Year
A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique
W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014
1542014
64-QAM 60-GHz CMOS transceivers for IEEE 802.11 ad/ay
R Wu, R Minami, Y Tsukui, S Kawai, Y Seo, S Sato, K Kimura, S Kondo, ...
IEEE Journal of Solid-State Circuits 52 (11), 2871-2891, 2017
1442017
A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration
A Musa, W Deng, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 49 (1), 50-60, 2013
1242013
A Low-Flicker-Noise 30-GHz Class-F23Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path
Y Hu, T Siriburanon, RB Staszewski
IEEE Journal of Solid-State Circuits 53 (7), 1977-1987, 2018
1222018
A 50.1-Gb/s 60-GHz CMOS transceiver for IEEE 802.11 ay with calibration of LO feedthrough and I/Q imbalance
J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ...
IEEE Journal of Solid-State Circuits 54 (5), 1375-1390, 2019
111*2019
A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad
T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ...
IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016
1082016
A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture
T Siriburanon, S Kondo, K Kimura, T Ueno, S Kawashima, T Kaneko, ...
IEEE Journal of Solid-State Circuits 51 (6), 1385-1397, 2016
792016
A sub-harmonic injection-locked quadrature frequency synthesizer with frequency calibration scheme for millimeter-wave TDD transceivers
W Deng, T Siriburanon, A Musa, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 48 (7), 1710-1720, 2013
732013
15.1 A 0.0066mm2780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique
W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
672014
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique
W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
612015
A 265- W Fractional- Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65 …
H Liu, Z Sun, H Huang, W Deng, T Siriburanon, J Pang, Y Wang, R Wu, ...
IEEE Journal of Solid-State Circuits 54 (12), 3478-3492, 2019
602019
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11 ay
R Wu, S Kawai, Y Seo, N Fajri, K Kimura, S Sato, S Kondo, T Ueno, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 248-249, 2016
572016
A 0.022mm2970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits
W Deng, A Musa, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
542013
A mixed-signal control core for a fully integrated semiconductor quantum computer system-on-chip
I Bashir, M Asker, C Cetintepe, D Leipold, A Esmailiyan, H Wang, ...
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
512019
Oscillator flicker phase noise: A tutorial
Y Hu, T Siriburanon, RB Staszewski
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 538-544, 2020
442020
A 60-GHz Sub-Sampling Frequency Synthesizer Using Sub-Harmonic Injection-Locked Quadrature Oscillators
T Siriburanon, T Ueno, K Kimura, S Kondo, W Deng, K Okada, ...
432014
17.6 A 21.7-to-26.5 GHz charge-sharing locking quadrature PLL with implicit digital frequency-tracking loop achieving 75fs jitter and− 250dB FoM
Y Hu, X Chen, T Siriburanon, J Du, Z Gao, V Govindaraj, A Zhu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2020
422020
A 0.5-V 1.6-mW 2.4-GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28-nm CMOS
N Pourmousavian, FW Kuo, T Siriburanon, M Babaie, RB Staszewski
IEEE Journal of Solid-State Circuits 53 (9), 2572-2583, 2018
412018
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular
T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
382015
A single-electron injection device for CMOS charge qubits implemented in 22-nm FD-SOI
I Bashir, E Blokhina, A Esmailiyan, D Leipold, M Asker, E Koskin, ...
IEEE Solid-State Circuits Letters 3, 206-209, 2020
332020
The system can't perform the operation now. Try again later.
Articles 1–20