Fumihiro Inoue
Fumihiro Inoue
確認したメール アドレス: imec.be
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引用先
Formation of electroless barrier and seed layers in a high aspect ratio through-Si vias using Au nanoparticle catalyst for all-wet Cu filling technology
F Inoue, T Shimizu, T Yokoyama, H Miyake, K Kondo, T Saito, T Hayashi, ...
Electrochimica Acta 56 (17), 6245-6250, 2011
532011
Perfect conformal deposition of electroless Cu for high aspect ratio through-Si vias
F Inoue, Y Harada, M Koyanagi, T Fukushima, K Yamamoto, S Tanaka, ...
Electrochemical and Solid State Letters 12 (10), H381, 2009
412009
Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias
F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, P Leunissen, ...
Electrochimica Acta 100, 203-211, 2013
402013
Electroless copper bath stability monitoring with UV-Vis spectroscopy, pH, and mixed potential measurements
F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, S Shingubara, ...
Journal of The Electrochemical Society 159 (7), D437, 2012
302012
Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias
F Inoue, T Shimizu, H Miyake, R Arima, T Ito, H Seki, Y Shinozaki, ...
Microelectronic engineering 106, 164-167, 2013
212013
3D stacking using bump-less process for sub 10um pitch interconnects
J Derakhshandeh, I De Preter, C Gerets, L Hou, N Heylen, E Beyne, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 128-133, 2016
172016
Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2Optical I/O
M Rakowski, Y Ban, P De Heyn, N Pantano, B Snyder, S Balakrishnan, ...
2018 IEEE Symposium on VLSI Technology, 221-222, 2018
142018
Investigation of advanced dicing technologies for ultra low-k and 3D integration
A Podpod, F Inoue, I De Wolf, M Gonzalez, MK Rebibis, RA Miller, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1247-1258, 2016
132016
Influence of Si wafer thinning processes on (sub) surface defects
F Inoue, A Jourdain, L Peng, A Phommahaxay, J De Vos, KJ Rebibis, ...
Applied Surface Science 404, 82-87, 2017
122017
Characterization of extreme Si thinning process for wafer-to-wafer stacking
F Inoue, A Jourdain, J De Vos, E Sleeckx, E Beyne, J Patel, O Ansell, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2095-2102, 2016
122016
3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ...
IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018
102018
Extreme wafer thinning optimization for via-last applications
A Jourdain, J De Vos, F Inoue, K Rebibis, A Miller, G Beyer, E Beyne, ...
2016 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2016
102016
Adsorption of Pd nanoparticles catalyst in high aspect ratio through-Si vias for electroless deposition
F Inoue, T Shimizu, H Miyake, R Arima, T Ito, H Seki, Y Shinozaki, ...
Electrochimica acta 82, 372-377, 2012
102012
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability
A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ...
2018 IEEE Symposium on VLSI Technology, 69-70, 2018
92018
RIE dynamics for extreme wafer thinning applications
N Rassoul, A Jourdain, N Tutunjyan, J De Vos, S Sardo, F Inoue, D Piumi, ...
Microelectronic engineering 192, 30-37, 2018
92018
Electroless Cu seed on Ru and Co liners in high aspect ratio TSV
F Inoue, H Philipsen, MH Van Der Veen, S Van Huylenbroeck, S Armini, ...
IEEE International Interconnect Technology Conference, 207-210, 2014
92014
Advances in sicn-sicn bonding with high accuracy wafer-to-wafer (w2w) stacking technology
L Peng, SW Kim, S Iacovo, F Inoue, A Phommahaxay, E Sleeckx, ...
2018 IEEE International Interconnect Technology Conference (IITC), 179-181, 2018
72018
3D IC assembly using thermal compression bonding and wafer-level underfill—Strategies for quality improvement and throughput enhancement
T Wang, P Bex, G Capuz, F Duval, F Inoue, C Gerets, J Bertheau, ...
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 791-796, 2016
72016
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ...
2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018
62018
Edge trimming for surface activated dielectric bonded wafers
F Inoue, A Jourdain, J Visker, L Peng, B Moeller, K Yokoyama, ...
Microelectronic Engineering 167, 10-16, 2017
62017
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