| Formation of electroless barrier and seed layers in a high aspect ratio through-Si vias using Au nanoparticle catalyst for all-wet Cu filling technology F Inoue, T Shimizu, T Yokoyama, H Miyake, K Kondo, T Saito, T Hayashi, ... Electrochimica Acta 56 (17), 6245-6250, 2011 | 66 | 2011 |
| Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, P Leunissen, ... Electrochimica Acta 100, 203-211, 2013 | 59 | 2013 |
| Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O M Rakowski, Y Ban, P De Heyn, N Pantano, B Snyder, S Balakrishnan, ... 2018 IEEE Symposium on VLSI Technology, 221-222, 2018 | 55 | 2018 |
| Perfect conformal deposition of electroless Cu for high aspect ratio through-Si vias F Inoue, Y Harada, M Koyanagi, T Fukushima, K Yamamoto, S Tanaka, ... Electrochemical and Solid-State Letters 12 (10), H381, 2009 | 47 | 2009 |
| Influence of composition of SiCN as interfacial layer on plasma activated direct bonding F Inoue, L Peng, S Iacovo, A Phommahaxay, P Verdonck, J Meersschaut, ... ECS Journal of Solid State Science and Technology 8 (6), P346, 2019 | 45 | 2019 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 38 | 2018 |
| Electroless copper bath stability monitoring with UV-Vis spectroscopy, pH, and mixed potential measurements F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, S Shingubara, ... Journal of The Electrochemical Society 159 (7), D437, 2012 | 34 | 2012 |
| Influence of Si wafer thinning processes on (sub) surface defects F Inoue, A Jourdain, L Peng, A Phommahaxay, J De Vos, KJ Rebibis, ... Applied Surface Science 404, 82-87, 2017 | 32 | 2017 |
| Advances in sicn-sicn bonding with high accuracy wafer-to-wafer (w2w) stacking technology L Peng, SW Kim, S Iacovo, F Inoue, A Phommahaxay, E Sleeckx, ... 2018 IEEE International Interconnect Technology Conference (IITC), 179-181, 2018 | 30 | 2018 |
| Enabling ultra-thin die to wafer hybrid bonding for future heterogeneous integrated systems A Phommahaxay, S Suhard, P Bex, S Iacovo, J Slabbekoorn, F Inoue, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 607-613, 2019 | 28 | 2019 |
| 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... 2018 IEEE Symposium on VLSI Technology, 69-70, 2018 | 28 | 2018 |
| 3D stacking using bump-less process for sub 10um pitch interconnects J Derakhshandeh, I De Preter, C Gerets, L Hou, N Heylen, E Beyne, ... 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 128-133, 2016 | 27 | 2016 |
| Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias F Inoue, T Shimizu, H Miyake, R Arima, T Ito, H Seki, Y Shinozaki, ... Microelectronic engineering 106, 164-167, 2013 | 27 | 2013 |
| 3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018 | 23 | 2018 |
| Characterization of extreme Si thinning process for wafer-to-wafer stacking F Inoue, A Jourdain, J De Vos, E Sleeckx, E Beyne, J Patel, O Ansell, ... 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2095-2102, 2016 | 19 | 2016 |
| Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling A Vandooren, L Witters, J Franco, A Mallik, B Parvais, Z Wu, A Walke, ... 2018 International Conference on IC Design & Technology (ICICDT), 145-148, 2018 | 17 | 2018 |
| Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications A Vandooren, Z Wu, A Khaled, J Franco, B Parvais, W Li, L Witters, ... 2019 Symposium on VLSI Technology, T56-T57, 2019 | 15 | 2019 |
| Extreme wafer thinning optimization for via-last applications A Jourdain, J De Vos, F Inoue, K Rebibis, A Miller, G Beyer, E Beyne, ... 2016 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2016 | 15 | 2016 |
| Semiconductor element and method of manufacturing the semiconductor element K Emura, F Inoue US Patent 8,592,954, 2013 | 15 | 2013 |
| Adsorption of Pd nanoparticles catalyst in high aspect ratio through-Si vias for electroless deposition F Inoue, T Shimizu, H Miyake, R Arima, T Ito, H Seki, Y Shinozaki, ... Electrochimica acta 82, 372-377, 2012 | 15 | 2012 |
shoso shingubaraKansai University確認したメール アドレス: kansai-u.ac.jp
