| Multiplexer-based array multipliers KZ Pekmestzi IEEE transactions on computers 48 (1), 15-23, 1999 | 103 | 1999 |
| Design-efficient approximate multiplication circuits through partial product perforation G Zervakis, K Tsoumanis, S Xydis, D Soudris, K Pekmestzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 73 | 2016 |
| An optimized modified booth recoder for efficient design of the add-multiply operator K Tsoumanis, S Xydis, C Efstathiou, N Moschopoulos, K Pekmestzi IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1133-1143, 2014 | 61 | 2014 |
| High performance and area efficient flexible DSP datapath synthesis S Xydis, G Economakos, D Soudris, K Pekmestzi IEEE transactions on very large scale integration (VLSI) systems 19 (3), 429-442, 2009 | 45 | 2009 |
| Pipelined array-based FIR filter folding P Bougas, P Kalivas, A Tsirikos, KZ Pekmestzi IEEE Transactions on Circuits and Systems I: Regular Papers 52 (1), 108-118, 2005 | 42 | 2005 |
| Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths S Xydis, G Economakos, K Pekmestzi Integration 42 (4), 486-503, 2009 | 38 | 2009 |
| Approximate hybrid high radix encoding for energy-efficient inexact multipliers V Leon, G Zervakis, D Soudris, K Pekmestzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 421-430, 2017 | 35 | 2017 |
| DONUT: A double node upset tolerant latch N Eftaxiopoulos, N Axelos, K Pekmestzi 2015 IEEE Computer Society Annual Symposium on VLSI, 509-514, 2015 | 35 | 2015 |
| Delta DICE: A double node upset resilient latch N Eftaxiopoulos, N Axelos, G Zervakis, K Tsoumanis, K Pekmestzi 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 34 | 2015 |
| Custom multi-threaded dynamic memory management for multiprocessor system-on-chip platforms S Xydis, A Bartzas, I Anagnostopoulos, D Soudris, K Pekmestzi 2010 International Conference on Embedded Computer Systems: Architectures …, 2010 | 33 | 2010 |
| On the hardware implementation of the 3GPP confidentiality and integrity algorithms K Marinis, NK Moshopoulos, F Karoubalis, KZ Pekmestzi International Conference on Information Security, 248-265, 2001 | 28 | 2001 |
| Complex number multipliers KZ Pekmestzi IEE Proceedings E (Computers and Digital Techniques) 136 (1), 70-75, 1989 | 27 | 1989 |
| Long unsigned number systolic serial multipliers and squarers KZ Pekmestzi, P Kalivas, N Moshopoulos IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 23 | 2001 |
| Flexible datapath synthesis through arithmetically optimized operation chaining S Xydis, I Triantafyllou, G Economakos, K Pekmestzi 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 407-414, 2009 | 21 | 2009 |
| Low-latency bit-parallel systolic VLSI implementation of FIR digital filters CG Caraiscos, KZ Pekmestzi IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1996 | 21 | 1996 |
| Walking through the energy-error Pareto frontier of approximate multipliers V Leon, G Zervakis, S Xydis, D Soudris, K Pekmestzi IEEE Micro 38 (4), 40-49, 2018 | 18 | 2018 |
| Systolic frequency dividers/counters KZ Pekmestzi, N Thanasouras IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1994 | 18 | 1994 |
| Low leakage radiation tolerant CAM/TCAM cell N Eftaxiopoulos, N Axelos, K Pekmestzi 2015 IEEE 21st International On-Line Testing Symposium (IOLTS), 206-211, 2015 | 17 | 2015 |
| Hybrid approximate multiplier architectures for improved power-accuracy trade-offs G Zervakis, S Xydis, K Tsoumanis, D Soudris, K Pekmestzi 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 16 | 2015 |
| A bisr architecture for embedded memories K Pekmestzi, N Axelos, I Sideris, N Moshopoulos 2008 14th IEEE International On-Line Testing Symposium, 149-154, 2008 | 16 | 2008 |
Sotirios XydisAssistant Professor, Harokopio University of AthensVerified email at hua.gr
