| Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs MA Aguilar, R Leupers, G Ascheid, LG Murillo Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 27 | 2016 |
| MAPS: A Software Development Environment for Embedded Multicore Applications. R Leupers, MA Aguilar, JF Eusse, J Castrillon, W Sheng Handbook of Hardware/Software Codesign, 917-949, 2017 | 19 | 2017 |
| Improving performance and productivity for software development on TI Multicore DSP platforms M Aguilar, R Jimenez, R Leupers, G Ascheid 2014 6th European Embedded Design in Education and Research Conference …, 2014 | 13 | 2014 |
| Software compilation techniques for heterogeneous embedded multi-core systems R Leupers, MA Aguilar, J Castrillon, W Sheng Handbook of Signal Processing Systems, 1021-1062, 2019 | 10 | 2019 |
| Parallelism Extraction in Embedded Software for Android Devices MA Aguilar, JF Eusse, P Ray, R Leupers, G Ascheid, W Sheng, P Sharma Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS …, 2015 | 10 | 2015 |
| Towards parallelism extraction for heterogeneous multicore android devices MA Aguilar, JF Eusse, P Ray, R Leupers, G Ascheid, W Sheng, P Sharma International Journal of Parallel Programming 45, 1592-1624, 2017 | 6 | 2017 |
| Unified identification of multiple forms of parallelism in embedded applications MA Aguilar, R Leupers 2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015 | 6 | 2015 |
| Automated code generation of streaming applications for C6000 multicore DSPs M Odendahl, W Sheng, M Aguilar, R Leupers, G Ascheid 2012 5th European DSP Education and Research Conference (EDERC), 221-224, 2012 | 6 | 2012 |
| Schedule-aware loop parallelization for embedded mpsocs by exploiting parallel slack MA Aguilar, R Leupers, G Ascheid, N Kavvadias, L Fitzpatrick Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 3 | 2017 |
| Extraction of kahn process networks from while loops in embedded software MA Aguilar, JF Eusse, R Leupers, G Ascheid, M Odendahl 2015 IEEE 17th International Conference on High Performance Computing and …, 2015 | 3 | 2015 |
| A toolflow for parallelization of embedded software in multicore DSP platforms MA Aguilar, R Leupers, G Ascheid, N Kavvadias Proceedings of the 18th International Workshop on Software and Compilers for …, 2015 | 3 | 2015 |
| Software Parallelization and Distribution for Heterogeneous Multi-Core Embedded Systems MAA Ulloa Rheinisch-Westfälische Technische Hochschule Aachen, 2018 | 2 | 2018 |
| Multi-grained performance estimation for MPSoC compilers: work-in-progress MA Aguilar, A Aggarwal, A Shaheen, R Leupers, G Ascheid, J Castrillon, ... Proceedings of the 2017 International Conference on Compilers, Architectures …, 2017 | 2 | 2017 |
| Extraction of recursion level parallelism for embedded multicore systems MA Aguilar, R Leupers, G Ascheid, JF Eusse 2017 International Conference on Embedded Computer Systems: Architectures …, 2017 | 2 | 2017 |
| Improving neural network architecture compression by multi-grain pruning K Kollek, MA Aguilar, M Braun, A Kummert 2021 IEEE International Conference on Progress in Informatics and Computing …, 2021 | 1 | 2021 |
| Work-in-progress: multi-grained performance estimation for MPSoC compilers MA Aguilar, A Aggarwal, A Shaheen, R Leupers, G Ascheid, J Castrillon, ... 2017 International Conference on Compilers, Architectures and Synthesis For …, 2017 | 1 | 2017 |
| Towards Effective Parallelization and Accelerator Offloading for Heterogeneous Multicore Embedded Systems MA Aguilar, R Leupers Proceedings of the 2016 International Summer School on Advanced Computer …, 2016 | 1 | 2016 |
| Desarrollo de una etapa de pre-procesamiento para reducción de ruido, mejoramiento de contraste y de nitidez en imágenes digitalizadas de geles de electroforesis MÁ Aguilar-Ulloa Instituto Tecnológico de Costa Rica. Escuela de Ingenieria Electronica., 2007 | 1 | 2007 |
| Retargeting MAPS to TI Multicore DSP Platforms for Real-Time Applications M Aguilar USI, Switzerland and RWTH Aachen University, Germany, 2012 | | 2012 |
| DISEÑO E IMPLEMENTACIÓN DE UN MICROPROCESADOR CON ARQUITECTURA SEGMENTADA EN FPGA JAD García, AM Madrigal, MA Aguilar Iberchip, Lima, Perú, 2007 | | 2007 |
Jeronimo CastrillonProfessor, TU Dresden確認したメール アドレス: tu-dresden.de
