Benjamin Sahelices
Benjamin Sahelices
Profesor de Informática, Universidad de Valladolid
確認したメール アドレス: infor.uva.es - ホームページ
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引用先
引用先
Volition: Scalable and precise sequential consistency violation detection
X Qian, J Torrellas, B Sahelices, D Qian
ACM SIGARCH Computer Architecture News 41 (1), 535-548, 2013
272013
OmniOrder: Directory-based conflict serialization of transactions
X Qian, B Sahelices, J Torrellas
ACM SIGARCH Computer Architecture News 42 (3), 421-432, 2014
212014
BulkSMT: Designing SMT processors for atomic-block execution
X Qian, B Sahelices, J Torrellas
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
132012
Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model
X Qian, H Huang, B Sahelices, D Qian
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
122013
Analysis and control of the intermediate memory states of RRAM devices by means of admittance parameters
H Castán, S Dueñas, H García, OG Ossorio, LA Domínguez, B Sahelices, ...
Journal of Applied Physics 124 (15), 152101, 2018
102018
A methodology to characterize critical section bottlenecks in dsm multiprocessors
B Sahelices, P Ibánez, V Viñals, JM Llabería
European Conference on Parallel Processing, 149-161, 2009
92009
BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment
X Qian, J Torrellas, B Sahelices, D Qian
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
72013
Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocol
X Qian, B Sahelices, D Qian
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
42014
Speeding-up synchronizations in dsm multiprocessors
A De Dios, B Sahelices, P Ibáñez, V Viñals, JM Llabería
European Conference on Parallel Processing, 473-484, 2006
42006
COMA-BC: una arquitectura de memoria sólo cache en bus común no jerárquica
BS Fernández
Universidad de Valladolid, 1998
31998
Aceleración del cambio de propietario de un cerrojo en multiprocesadores DSM
E Rodríguez, B Sahelices, DR Llanos, P Ibáñez, V Viñals, JM Llabería
Proc. XVIII Jornadas de Paralelismo, 139-146, 2007
22007
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers
B Sahelices, A de Dios, P Ibáñez, V Vinals-Yufera, JM Llabería
Journal of Computer Science and Technology 27 (1), 75-91, 2012
12012
Thermoelectrical characterization of piezoelectric diaphragms: towards a betterunderstanding of ferroelectrics for future memory applications
G Vinuesa, P Marín, OG Ossorio, B Sahelices, H Garcia, H Castan, ...
239th ECS Meeting with the 18th International Meeting on Chemical Sensors …, 2021
2021
Evaluación de optimizaciones hardware de sincronización en multiprocesadores cc-NUMA
DB Sahelices, DDR Llanos
2008
Speeding-Up Synchronization in DSM Multiprocessors
B Sahelices, I Pablo, V Víctor, JM Llabería
2006
Topic 7-Parallel Computer Architecture and Instruction Level Parallelism-Speeding-Up Synchronizations in DSM Multiprocessors
A Dios, B Sahelices, P Ibanez, V Vinals, JM Llaberia
Lecture Notes in Computer Science 4128, 473-484, 2006
2006
Autoinvalidación Mejorada Utilizando Predicción deUltimo Toque
B Sahelices, A de Dios, P Ibánez, V Vinals, JM Llaberıa
Caracterización de Secciones Crıticas SPLASH-2 en Multiprocesadores DSM
B Sahelices, E Rodrıguez, P Ibanez, V Vinals, JM Llaberıa
Reducción de la Latencia de Lectura Mediante Predicción deUltima Escritura en Multiprocesadores
B Sahelices, A de Dios, P Ibánez, V Vinals, JM Llaberıa
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論文 1–19