| A dynamically reconfigurable processor architecture M Motomura Microprocessor Forum, 2002, 2002 | 221 | 2002 |
| BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 185 | 2017 |
| Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same M Motomura US Patent 6,172,521, 2001 | 181 | 2001 |
| Line buffer type semiconductor memory device capable of direct prefetch and restore operations M Motomura US Patent 6,347,055, 2002 | 167 | 2002 |
| Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads M Motomura US Patent 5,742,822, 1998 | 136 | 1998 |
| Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof M Motomura US Patent 6,338,108, 2002 | 119 | 2002 |
| A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture T Fujii, K Furuta, M Motomura, M Nomura, M Mizuno, K Anjo, ... 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 113 | 1999 |
| QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018 | 104 | 2018 |
| Array type processor with state transition controller identifying switch configuration and processing element instruction address T Fujii, M Motomura, K Furuta US Patent 6,738,891, 2004 | 104 | 2004 |
| BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 97 | 2017 |
| STATICA: A 512-spin 0.25 M-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin–spin interactions K Yamamoto, K Kawamura, K Ando, N Mertig, T Takemoto, M Yamaoka, ... IEEE Journal of Solid-State Circuits 56 (1), 165-178, 2020 | 85 | 2020 |
| A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM M Motomura, J Toyoura, K Hirata, H Ooka, H Yamada, T Enomoto IEEE Journal of Solid-State Circuits 25 (5), 1158-1165, 1990 | 75 | 1990 |
| Memory integrated circuit and main memory and graphics memory systems applying the above M Motomura, Y Yabe, Y Aimoto US Patent 6,263,413, 2001 | 74 | 2001 |
| An embedded DRAM-FPGA chip with instantaneous logic reconfiguration M Motomura, Y Aimoto, A Shibayama, Y Yabe, M Yamashina Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No …, 1998 | 70 | 1998 |
| Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS M Miyamura, S Nakaya, M Tada, T Sakamoto, K Okamoto, N Banno, ... 2011 IEEE International Solid-State Circuits Conference, 228-229, 2011 | 62 | 2011 |
| Programmable device with an array of programmable cells and interconnection network K Furuta, T Fujii, M Motomura US Patent 6,281,703, 2001 | 61 | 2001 |
| A 7.68 gips 3.84 gb/s 1w parallel image processing ram integrating a 16 mb dram and 128 processors Y Aimoto, T Kimura, Y Yabe, H Heiuchi, Y Nakazawa, M Motomura, ... 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical …, 1996 | 61 | 1996 |
| QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ... IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018 | 60 | 2018 |
| Stream applications on the dynamically reconfigurable processor M Suzuki, Y Hasegawa, Y Yamada, N Kaneko, K Deguchi, H Amano, ... Proceedings. 2004 IEEE International Conference on Field-Programmable …, 2004 | 60 | 2004 |
| A memory-based realization of a binarized deep convolutional neural network H Nakahara, H Yonekawa, T Sasao, H Iwamoto, M Motomura 2016 International Conference on Field-Programmable Technology (FPT), 277-280, 2016 | 56 | 2016 |
