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masato motomura
masato motomura
Tokyo Institute of Technology
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A dynamically reconfigurable processor architecture
M Motomura
Microprocessor Forum, Oct. 2002, 2002
2212002
Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same
M Motomura
US Patent 6,172,521, 2001
1812001
BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ...
IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017
1672017
Line buffer type semiconductor memory device capable of direct prefetch and restore operations
M Motomura
US Patent 6,347,055, 2002
1672002
Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads
M Motomura
US Patent 5,742,822, 1998
1331998
Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof
M Motomura
US Patent 6,338,108, 2002
1192002
A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture
T Fujii, K Furuta, M Motomura, M Nomura, M Mizuno, K Anjo, ...
1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999
1161999
Array type processor with state transition controller identifying switch configuration and processing element instruction address
T Fujii, M Motomura, K Furuta
US Patent 6,738,891, 2004
1032004
QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018
1002018
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ...
2017 Symposium on VLSI Circuits, C24-C25, 2017
932017
A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM
M Motomura, J Toyoura, K Hirata, H Ooka, H Yamada, T Enomoto
IEEE Journal of Solid-State Circuits 25 (5), 1158-1165, 1990
741990
Memory integrated circuit and main memory and graphics memory systems applying the above
M Motomura, Y Yabe, Y Aimoto
US Patent 6,263,413, 2001
732001
An embedded DRAM-FPGA chip with instantaneous logic reconfiguration
M Motomura, Y Aimoto, A Shibayama, Y Yabe, M Yamashina
Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No …, 1998
721998
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS
M Miyamura, S Nakaya, M Tada, T Sakamoto, K Okamoto, N Banno, ...
2011 IEEE International Solid-State Circuits Conference, 228-229, 2011
622011
STATICA: A 512-spin 0.25 M-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin–spin interactions
K Yamamoto, K Kawamura, K Ando, N Mertig, T Takemoto, M Yamaoka, ...
IEEE Journal of Solid-State Circuits 56 (1), 165-178, 2020
612020
Programmable device with an array of programmable cells and interconnection network
K Furuta, T Fujii, M Motomura
US Patent 6,281,703, 2001
612001
QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS
K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ...
IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018
582018
Stream applications on the dynamically reconfigurable processor
M Suzuki, Y Hasegawa, Y Yamada, N Kaneko, K Deguchi, H Amano, ...
Proceedings. 2004 IEEE International Conference on Field-Programmable …, 2004
582004
A 7.68 gips 3.84 gb/s 1w parallel image processing ram integrating a 16 mb dram and 128 processors
Y Aimoto, T Kimura, Y Yabe, H Heiuchi, Y Nakazawa, M Motomura, ...
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical …, 1996
581996
A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution
N Nishi, T Inoue, M Nomura, S Matsushita, S Torii, A Shibayama, J Sakai, ...
2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000
532000
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