| The impact of RTN on performance fluctuation in CMOS logic circuits K Ito, T Matsumoto, S Nishizawa, H Sunagawa, K Kobayashi, H Onodera Reliability Physics Symposium (IRPS), 2011 IEEE International, CR. 5.1-CR. 5.4, 2011 | 54 | 2011 |
| Modeling of random telegraph noise under circuit operation—Simulation and measurement of RTN-induced delay fluctuation K Ito, T Matsumoto, S Nishizawa, H Sunagawa, K Kobayashi, H Onodera 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 36 | 2011 |
| NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map YL Li, ST Lin, S Nishizawa, HY Su, MJ Fong, O Chen, H Onodera Proceedings of the 56th Annual Design Automation Conference 2019, 120, 2019 | 31 | 2019 |
| Analysis and comparison of XOR cell structures for low voltage circuit design S Nishizawa, T Ishihara, H Onodera International Symposium on Quality Electronic Design (ISQED), 703-708, 2013 | 28 | 2013 |
| MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing YL Li, ST Lin, S Nishizawa, H Onodera 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2020 | 12 | 2020 |
| A flexible structure of standard cell and its optimization method for near-threshold voltage operation S Nishizawa, T Ishihara, H Onodera 2012 IEEE 30th International Conference on Computer Design (ICCD), 235-240, 2012 | 7 | 2012 |
| A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop S Nishizawa, H Onodera IEEE Transactions on Semiconductor Manufacturing, 26 (3), 306-313, 2013 | 6 | 2013 |
| Pin accessibility evaluating model for improving routability of VLSI designs HY Su, S Nishizawa, YS Wu, J Shiomi, YL Li, H Onodera 2017 30th IEEE International System-on-Chip Conference (SOCC), 56-61, 2017 | 5 | 2017 |
| Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier M Zhang, S Nishizawa, S Kimura IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 4 | 2023 |
| libretto: An Open Cell Timing Characterizer for Open Source VLSI Design S NISHIZAWA, T NAKURA IEICE Transactions on Fundamentals of Electronics, Communications and …, 2022 | 4 | 2022 |
| Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits AKMM Islam, S Nishizawa, Y Matsui, Y Ichida 20th International Symposium on Quality Electronic Design (ISQED), 298-303, 2019 | 4 | 2019 |
| Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution K ITO, Y ISHIHARA, S NISHIZAWA IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2018 | 4 | 2018 |
| Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell S Nishizawa, T Ishihara, H Onodera IPSJ Transactions on System LSI Design Methodology 8, 131-135, 2015 | 4 | 2015 |
| A Standard Cell Optimization Method for Near-Threshold Voltage Operations M Kondo, S Nishizawa, T Ishihara, H Onodera Integrated Circuit and System Design. Power and Timing Modeling …, 2012 | 4 | 2012 |
| Compact Modeling of NBTI Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement T Hosaka, S Nishizawa, R Kishida, T Matsumoto, K Kobayashi 2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019 | 3 | 2019 |
| Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation S Nishizawa, T Ishihara, H Onodera 2014 27th IEEE International System-on-Chip Conference (SOCC), 42-47, 2014 | 3 | 2014 |
| Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics T Konno, S Nishizawa, K Ito 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS …, 2018 | 2 | 2018 |
| Variation-aware Flip-Flop energy optimization for ultra low voltage operation T Kamakari, S Nishizawa, T Ishihara, H Onodera 2014 27th IEEE International System-on-Chip Conference (SOCC), 17-22, 2014 | 2 | 2014 |
| Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks M Zhang, K Ma, R Duan, S Nishizawa, S Kimura 2023 IEEE 36th International System-on-Chip Conference (SOCC), 1-6, 2023 | 1 | 2023 |
| Supplemental PDK for ASAP7 Using Synopsys Flow S Nishizawa, ST Lin, YL Li, H Onodera IPSJ Transactions on System LSI Design Methodology 14, 24-26, 2021 | 1 | 2021 |
Tohru IshiharaProfessor of Nagoya UniversityVerified email at ertl.jp
