| Em attack is non-invasive?-design methodology and validity verification of em attack sensor N Homma, Y Hayashi, N Miura, D Fujimoto, D Tanaka, M Nagata, T Aoki Cryptographic Hardware and Embedded Systems–CHES 2014: 16th International …, 2014 | 65 | 2014 |
| A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor N Miura, D Fujimoto, D Tanaka, Y Hayashi, N Homma, T Aoki, M Nagata 2014 symposium on VLSI circuits digest of technical papers, 1-2, 2014 | 43 | 2014 |
| 12.4 A 1mm-pitch 80× 80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan N Miura, S Dosho, S Takaya, D Fujimoto, T Kiriyama, H Tezuka, T Miki, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 37* | 2014 |
| EM information security threats against RO-based TRNGs: The frequency injection attack based on IEMI and EM information leakage S Osuka, D Fujimoto, Y Hayashi, N Homma, A Beckers, J Balasch, ... IEEE Transactions on Electromagnetic Compatibility 61 (4), 1122-1128, 2018 | 24 | 2018 |
| A silicon-level countermeasure against fault sensitivity analysis and its evaluation S Endo, Y Li, N Homma, K Sakiyama, K Ohta, D Fujimoto, M Nagata, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8 …, 2014 | 23 | 2014 |
| A demonstration of a HT-detection method based on impedance measurements of the wiring around ICs D Fujimoto, S Nin, YI Hayashi, N Miura, M Nagata, T Matsumoto IEEE Transactions on Circuits and Systems II: Express Briefs 65 (10), 1320-1324, 2018 | 22 | 2018 |
| Design methodology and validity verification for a reactive countermeasure against EM attacks N Homma, Y Hayashi, N Miura, D Fujimoto, M Nagata, T Aoki Journal of Cryptology 30, 373-391, 2017 | 21 | 2017 |
| Physical security evaluation at an early design-phase: A side-channel aware simulation methodology S Bhasin, JL Danger, T Graba, Y Mathieu, D Fujimoto, M Nagata Proceedings of International Workshop on Engineering Simulations for Cyber …, 2013 | 20 | 2013 |
| An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor N Miura, D Fujimoto, R Korenaga, K Matsuda, M Nagata 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 225-228, 2014 | 18 | 2014 |
| Side-channel leakage on silicon substrate of CMOS cryptographic chip D Fujimoto, D Tanaka, N Miura, M Nagata, Y Hayashi, N Homma, ... 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 18 | 2014 |
| Electromagnetic information extortion from electronic devices using interceptor and its countermeasure M Kinugawa, D Fujimoto, Y Hayashi IACR Transactions on Cryptographic Hardware and Embedded Systems, 62-90, 2019 | 17 | 2019 |
| Simulation techniques for EMC compliant design of automotive IC chips and modules A Tsukioka, M Nagata, K Taniguchi, D Fujimoto, R Akimoto, T Egami, ... 2017 International Symposium on Electromagnetic Compatibility-EMC EUROPE, 1-6, 2017 | 16 | 2017 |
| Detection of IEMI fault injection using voltage monitor constructed with fully digital circuit D Fujimoto, Y Hayashi, A Beckers, J Balasch, B Gierlichs, I Verbauwhede 2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 …, 2018 | 15 | 2018 |
| Characterization of EM faults on ATmega328p A Beckers, J Balasch, B Gierlichs, I Verbauwhede, S Osuka, M Kinugawa, ... 2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo …, 2019 | 14 | 2019 |
| Data injection attack against electronic devices with locally weakened immunity using a hardware Trojan S Kaji, M Kinugawa, D Fujimoto, Y Hayashi IEEE Transactions on Electromagnetic Compatibility 61 (4), 1115-1121, 2018 | 14 | 2018 |
| A fast power current analysis methodology using capacitor charging model for side channel attack evaluation D Fujimoto, M Nagata, T Katashita, A Sasaki, Y Hori, A Satoh 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, 87-92, 2011 | 14 | 2011 |
| Design considerations for EM pulse fault injection A Beckers, M Kinugawa, Y Hayashi, D Fujimoto, J Balasch, B Gierlichs, ... Smart Card Research and Advanced Applications: 18th International Conference …, 2020 | 13 | 2020 |
| On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis D Fujimoto, N Miura, M Nagata, Y Hayashi, N Homma, Y Hori, T Katashita, ... 2013 International Symposium on Electromagnetic Compatibility, 405-410, 2013 | 13 | 2013 |
| EM attack sensor: Concept, circuit, and design-automation methodology N Miura, D Fujimoto, M Nagata, N Homma, Y Hayashi, T Aoki Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 12 | 2015 |
| On-chip monitor circuit and semiconductor chip M Nagata, JL Danger, D Fujimoto, S Bhasin US Patent 10,776,484, 2020 | 11 | 2020 |
Yu-ichi HAYASHINara Institute of Science and Technology確認したメール アドレス: is.naist.jp
