Vamsi Paruchuri
Vamsi Paruchuri
ASM, IBM Research, University of Utah
確認したメール アドレス: asm.com
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引用先
引用先
A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates
S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006
2452006
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ...
2017 Symposium on VLSI Technology, T230-T231, 2017
1952017
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
H Kawasaki, VS Basker, T Yamashita, CH Lin, Y Zhu, J Faltermeier, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
1632009
Hafnium oxide gate dielectrics on sulfur-passivated germanium
MM Frank, SJ Koester, M Copel, JA Ott, VK Paruchuri, H Shang, ...
Applied Physics Letters 89 (11), 112905, 2006
1602006
Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos
NA Bojarczuk, MP Chudzik, MW Copel, S Guha, R Jammy, V Narayanan, ...
US Patent App. 12/166,690, 2008
1202008
Examination of flatband and threshold voltage tuning of field effect transistors by dielectric cap layers
S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, ...
Applied Physics Letters 90 (9), 092902, 2007
1162007
Metal gate CMOS with at least a single gate metal and dual gate dielectrics
BB Doris, YH Kim, BP Linder, V Narayanan, VK Paruchuri
US Patent 7,432,567, 2008
1112008
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011
1092011
A 0.063 µm2FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
VS Basker, T Standaert, H Kawasaki, CC Yeh, K Maitra, T Yamashita, ...
2010 Symposium on VLSI Technology, 19-20, 2010
1092010
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ...
2007 IEEE Symposium on VLSI Technology, 194-195, 2007
1092007
Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2
E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005
1022005
High performance CMOS circuits, and methods for fabricating the same
J Arnold, G Biery, A Callegari, TC Chen, M Chudzik, B Doris, M Gribelyuk, ...
US Patent App. 11/323,578, 2007
972007
Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond
TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006
962006
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ...
2010 Symposium on VLSI Technology, 57-58, 2010
932010
Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack
E Cartier, BP Linder, V Narayanan, VK Paruchuri
2006 International Electron Devices Meeting, 1-4, 2006
912006
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ...
2016 IEEE International Electron Devices Meeting (IEDM), 2.7. 1-2.7. 4, 2016
872016
Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
NA Bojarczuk Jr, C Cabral Jr, EA Cartier, MW Copel, MM Frank, ...
US Patent 7,105,889, 2006
852006
22 nm technology compatible fully functional 0.1 μm26T-SRAM cell
BS Haran, A Kumar, L Adam, J Chang, V Basker, S Kanakasabapathy, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
842008
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
792014
Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
NA Bojarczuk Jr, C Cabral Jr, EA Cartier, MW Copel, MM Frank, ...
US Patent 7,479,683, 2009
732009
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