| SigRace: signature-based data race detection A Muzahid, D Suárez, S Qi, J Torrellas ACM SIGARCH Computer Architecture News 37 (3), 337-348, 2009 | 120 | 2009 |
| Directed event signaling for multiprocessor systems DS Gracia, H Zhao, PM Ortego, GC Cascaval, J Xenidis US Patent 9,632,569, 2017 | 36 | 2017 |
| Methods and systems for detecting malware and attacks that target behavioral security mechanisms of a mobile device DS Garcia, R Gupta, A Gantman US Patent 9,357,397, 2016 | 35 | 2016 |
| Software Configurations for Mobile Devices in a Collaborative Environment H Chao, DS Gracia, GC Cascaval US Patent App. 14/300,407, 2015 | 27 | 2015 |
| LP-NUCA: Networks-in-cache for high-performance low-power embedded processors DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011 | 22 | 2011 |
| Concertina: Squeezing in cache content to operate at near-threshold voltage A Ferreron, D Suarez-Gracia, J Alastruey-Benede, T Monreal-Arnal, ... IEEE Transactions on Computers 65 (3), 755-769, 2015 | 18 | 2015 |
| Simultaneous multiprocessing in a software-defined heterogeneous FPGA J Nunez-Yanez, S Amiri, M Hosseinabady, A Rodríguez, R Asenjo, ... The Journal of Supercomputing 75 (8), 4078-4095, 2019 | 14 | 2019 |
| Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL MAD Guzman, R Nozal, RG Tejero, M Villarroya-Gaudo, DS Gracia, ... The Journal of Supercomputing 75 (3), 1732-1746, 2019 | 11 | 2019 |
| Data management for multiple processing units using data transfer costs DS Gracia, T Kumar, A Natarajan, R Hastantram, GC Cascaval, H Zhao US Patent 9,733,978, 2017 | 11 | 2017 |
| Analysis of network-on-chip topologies for cost-efficient chip multiprocessors M Ortín-Obón, D Suárez-Gracia, M Villarroya-Gaudó, C Izu, ... Microprocessors and Microsystems 42, 24-36, 2016 | 11 | 2016 |
| Automatic discovery of performance and energy pitfalls in html and css A Sampson, C Caşcaval, L Ceze, P Montesinos, DS Gracia 2012 IEEE International Symposium on Workload Characterization (IISWC), 82-83, 2012 | 11 | 2012 |
| A proposal to introduce power and energy notions in computer architecture laboratories AA Pérez, DS Gracia, VV Yúfera Proceedings of the 2007 workshop on Computer architecture education, 52-57, 2007 | 11 | 2007 |
| Light NUCA: a proposal for bridging the inter-cache latency gap D Suárez, T Monreal Arnal, F Vallejo, JR Beivide Palacio, V Viñals Yufera Design, Automation and Test in Europe 2009, 530-535, 2009 | 10 | 2009 |
| Random-access disjoint concurrent sparse writes to heterogeneous buffers T Kumar, A Natarajan, DS Gracia US Patent 10,031,697, 2018 | 8* | 2018 |
| Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ... The Journal of Supercomputing, 1-21, 2019 | 7 | 2019 |
| Processor Energy and Temperature in Computer Architecture Courses: a hands-on approach S Gutiérrez-Verde, O Benedı-Sánchez, D Suárez-Gracia, ... Workshop on Computer Architecture Education, 2009 | 7 | 2009 |
| Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ... Journal of Systems Architecture 98, 27-40, 2019 | 6 | 2019 |
| Proactive resource management for parallel work-stealing processing systems H Zhao, DS Gracia, T Kumar US Patent 10,360,063, 2019 | 6 | 2019 |
| Block disabling characterization and improvements in CMPs operating at ultra-low voltages A Ferrerón, D Suarez-Gracia, J Alastruey-Benedé, T Monreal, V Vinals 2014 IEEE 26th International Symposium on Computer Architecture and High …, 2014 | 6 | 2014 |
| A comparison of cache hierarchies for SMT processors D Suárez, T Monreal, V Vinals Proc. of the 22nd Jornadas de Paralelismo, 2011 | 6 | 2011 |
Víctor Viñals-YúferaUniversidad de Zaragoza確認したメール アドレス: unizar.es
