フォロー
Tsutomu Yoshimura
Tsutomu Yoshimura
Osaka Institute of Technology
確認したメール アドレス: oit.ac.jp - ホームページ
タイトル
引用先
引用先
Delay locked loop circuit
T Yoshimura, Y Nakase, Y Morooka, N Watanabe, H Kondoh, H Notani
US Patent 5,994,934, 1999
991999
A 622-mb/s bit/frame synchronizer for high-speed backplane data communication
T Yoshimura, H Kondoh, Y Matsuda, T Sumi
IEEE Journal of Solid-State Circuits 31 (7), 1063-1066, 1996
661996
A 622-mb/s bit/frame synchronizer for high-speed backplane data communication
T Yoshimura, H Kondoh, Y Matsuda, T Sumi
IEEE Journal of Solid-State Circuits 31 (7), 1063-1066, 1996
661996
Automatic frequency correction PLL circuit
T Yoshimura
US Patent 7,519,140, 2009
602009
Duty-ratio correction circuit and clock generation circuit
T Yoshimura
US Patent 6,198,322, 2001
412001
Clock generator for generating internal clock signal synchronized with reference clock signal
R Mano, T Yoshimura
US Patent 6,570,456, 2003
282003
A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories
T Yoshimura, Y Nakase, N Watanabe, Y Morooka, Y Matsuda, ...
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998
221998
Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop
T Yoshimura, S Iwade, H Makino, Y Matsuda
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (4), 896-907, 2012
202012
Digital synchronous circuit for stably generating output clock synchronized with input data
T Yoshimura, H Kondoh
US Patent 6,987,825, 2006
132006
A 10 Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 µm SOI/CMOS Technology
T Yoshimura, K Ueda, J Takasoh, H KONDOH
IEICE transactions on electronics 86 (4), 643-651, 2003
132003
Voltage controlled oscillator including a plurality of differential amplifiers
T Yoshimura
US Patent 6,252,467, 2001
132001
Ninety-degree phase shifter
T Yoshimura, Y Nakase, Y Morooka, N Watanabe
US Patent 6,160,434, 2000
122000
Differential charge pump circuit
T Yoshimura
US Patent 7,250,808, 2007
102007
Spur reduction by self-injection loop in a fractional-N PLL
M Kobayashi, Y Masui, T Kihara, T Yoshimura
2017 24th IEEE International Conference on Electronics, Circuits and Systems …, 2017
62017
基礎電気回路
伊佐弘, 谷口勝則, 岩井嘉男, 吉村勉, 見市知昭
Morikita Shuppan Kabushiki Kaisha, 2017
62017
A study of interference in synchronous systems
T Yoshimura, A Iwata
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (8), 1726-1740, 2006
62006
Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same
T Yoshimura
US Patent 6,707,319, 2004
62004
Analysis and modeling of response of external noise in oscillators
T Yoshimura, T Kihara
Analog Integrated Circuits and Signal Processing 87, 313-325, 2016
42016
A 2.6 GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection
N Fujii, S Morishita, T Kihara, T Yoshimura
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016
32016
Analysis and modeling of oscillators with interference noise
S Shimizu, J Mizuno, S Morishita, K Hida, T Yoshimura
2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014
32014
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論文 1–20