Rutile-type TiO2 thin film for high-k gate insulator M Kadoshima, M Hiratani, Y Shimamoto, K Torii, H Miki, S Kimura, ... Thin Solid Films 424 (2), 224-228, 2003 | 306 | 2003 |
Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control R Tsuchiya, M Horiuchi, S Kimura, M Yamaoka, T Kawahara, S Maegawa, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 195 | 2004 |
The effect of a grain boundary structural transformation on sliding in< 1010>-tilt zinc bicrystals T Watanabe, SI Kimura, S Karashima Philosophical Magazine A 49 (6), 845-864, 1984 | 158 | 1984 |
Semiconductor device N Sugll, R Tsuchiya, S Kimura US Patent App. 12/187,504, 2009 | 150 | 2009 |
Promising storage capacitor structures with thin Ta/sub 2/O/sub 5/film for low-power high-density DRAMs H Shinriki, T Kisu, SI Kimura, Y Nishioka, Y Kawamoto, K Mukai IEEE Transactions on Electron Devices 37 (9), 1939-1947, 1990 | 149 | 1990 |
Semiconductor integrated circuit device and process for manufacturing the same S Yamada, K Oyu, S Kimura US Patent 6,770,535, 2004 | 145 | 2004 |
Semiconductor memory device having stacked capacitor cells S Kimura, N Hashimoto, Y Sakai, T Kure, Y Kawamoto US Patent 4,970,564, 1990 | 141 | 1990 |
Limitations and challenges of multigigabit DRAM chip design K Itoh, Y Nakagome, S Kimura, T Watanabe IEEE Journal of Solid-State Circuits 32 (5), 624-634, 1997 | 136 | 1997 |
Dynamic random access memory having trench capacitors and vertical transistors S Kimura, T Kure, T Kaga, D Hisamoto, E Takeda US Patent 5,177,576, 1993 | 131 | 1993 |
Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology M Yamaoka, K Osada, R Tsuchiya, M Horiuchi, S Kimura, T Kawahara 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 130 | 2004 |
LocalVariability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation N Sugii, R Tsuchiya, T Ishigaki, Y Morita, H Yoshimoto, S Kimura IEEE Transactions on Electron Devices 57 (4), 835-845, 2010 | 115 | 2010 |
Low Temperature Oxidation of Silicon in a Microwave‐Discharged Oxygen Plasma S Kimura, E Murakami, K Miyake, T Warabisako, H Sunami, T Tokuyama Journal of the Electrochemical Society 132 (6), 1460, 1985 | 112 | 1985 |
Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate N Sugii, D Hisamoto, K Washio, N Yokoyama, S Kimura IEEE Transactions on Electron Devices 49 (12), 2237-2243, 2002 | 110 | 2002 |
Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode D Hisamoto, S Shukuri, K Sagara, S Kimura, S Minami, E Takeda US Patent 5,355,330, 1994 | 110 | 1994 |
Process for producing memory cell having stacked capacitor S Kimura, H Sunami US Patent 4,742,018, 1988 | 110 | 1988 |
Method of manufacturing a semiconductor device having silicon islands D Hisamoto, T Kaga, S Kimura, M Moniwa, H Tanaka, A Hiraiwa, ... US Patent 5,466,621, 1995 | 103 | 1995 |
Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics S Tsujikawa, T Mine, K Watanabe, Y Shimamoto, R Tsuchiya, K Ohnishi, ... 2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003 | 101 | 2003 |
Leakage‐Current Increase in Amorphous Ta2 O 5 Films Due to Pinhole Growth during Annealing Below 600° C S Kimura, Y Nishioka, A Shintani, K Mukai Journal of the Electrochemical Society 130 (12), 2414, 1983 | 94 | 1983 |
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme H Tanaka, M Aoki, T Sakata, S Kimura, N Sakashita, H Hidaka, ... IEEE Journal of Solid-State Circuits 34 (8), 1084-1090, 1999 | 93 | 1999 |
Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate Y Morita, R Tsuchiya, T Ishigaki, N Sugii, T Iwamatsu, T Ipposhi, H Oda, ... 2008 Symposium on VLSI Technology, 166-167, 2008 | 92 | 2008 |